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Recommendations for System Design
The goal of the LIN physical layer standard is to have a
universal definition of the LIN system for plug and play
solutions in LIN networks up to 20 kBd bus speeds.
In case of small and medium LIN networks, it’s
recommended to adjust the total network capacitance to at
least 4.0 nF for good EMC and EMI behavior. This can be
done by setting only the master node capacitance. The
slave node capacitance should have a unit load of typically
220 pF for good EMC/EMI behavior.
In large networks with long bus lines and the maximum
number of nodes, some system parameters can exceed the
defined limits and the LIN system designer must intervene.
The whole capacitance of a slave node is not only the unit
load capacitor itself. Additionally, there is the capacitance
of wires and connectors, and the internal capacitance of the
LIN transmitter. This internal capacitance is strongly
dependent on the technology of the IC manufacturer and
should be in the range of 30 pF to 150 pF. If the bus lines
have a total length of nearly 40m, the total bus capacitance
can exceed the LIN system limit of 10 nF.
A second parameter of concern is the integrated slave
termination resistor tolerance. If most of the slave nodes
have a slave termination resistance at the allowed
maximum of 60 k, the total network resistance is more
than 700 . Even if the total network capacitance is below
or equal to the maximum specified value of 10 nF, the
network time constant is higher than 7.0 s.
This problem can be solved only by adjusting the master
termination resistor to the required maximum network time
constant of 5.0 s (max).
NOTE: The NCV7380 meets the requirements for
implementation in RCbased slave nodes. The LIN
Protocol Specification requires the deviation of the slave
node clock to the master node clock after synchronization
must not differ by more than "2%.
Setting the network time constant is necessary in large
networks (primarily resistance) and also in small networks
(primarily capacitance).
MIN/MAX SLOPE TIME CALCULATION
(In accordance to the LIN System Parameter Table)
Figure 7. Slope Time and Slew Rate Calculation
(In accordance to LIN physical layer specification 1.3)
60%
100%
0%
t
srec
t
sdom
V
BUS
40%
V
dom
60%
40%
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
dVńdt + 0.2 * V
swing
ń(t
40%
t
60%
)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
t
slope
+ 5*(t
40%
t
60%
)
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
t
slope
+ V
swing
ńdVńdt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because it’s
a passive edge. In case of low battery voltages and high bus
loads the rising edge is only determined by the network. If the
rising edge slew rate exceeds the value of the dominant one,
the slew rate control determines the rising edge.
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Figure 8. Duty Cycle Measurement and Calculation in Accordance to LIN Physical Layer Specification 2.0
V
SUP
TxD
RxD
BUS
GND
t
Bit
t
Bit
100%
t
dom(max)
t
dom(min)
58.1%
28.4%
74.4%
42.2%
t
rec(max)
58.1%
28.4%
t
rec(min)
0%
Duty Cycle Calculation
With the timing parameters shown in Figure 8 two duty
cycles, based on t
rec(min)
and t
rec(max)
can be calculated as
follows:
D1* = t
rec(min)
/(2 x t
Bit
)
D2* = t
rec(max)
/(2 x t
Bit
)
For proper operation at 20 KBit/s (bit time is 50 s) the
LIN driver has to fulfill the duty cycles specified in the AC
characteristics for supply voltages of 7...18 V and the three
defined standard loads.
Due to this simple definition there is no need to measure
slew rates, slope times, transmitter delays and dominant
voltage levels as specified in the LIN physical layer
specification 1.3.
The devices within the D1/D2 duty cycle range also
operates in applications with reduced bus speed of
10.4 kBit/s or below.
In order to minimize EME, the slew rates of the
transmitter can be reduced (by up to [ 2 times). Such
devices have to fulfill the duty cycle definition D3/D4 in
the LIN physical layer specification 2.0. Devices within
this duty cycle range cannot operate in higher frequency
20 kBit/s applications.
*D1 and D2 are defined in the LIN protocol specification 2.0.
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Ignition
Car Battery
V
BAT
1N4001
Voltage
Regulator
NCV8502
V
OUT
10 k
47 nF
100 nF
mP
GND
2.7 K
NCV7380
RxD
TxD
GND
VCC VS
BUS
2.2 F
100 nF
Slave
ECU
LIN BUS
220 pF
ECU Connector
to Single Wire
LIN Bus
V
BAT
1N4001
Voltage
Regulator
NCV8501
47 nF
mP
GND
2.7 K
NCV7382
*
RxD
GND
VCC VS
BUS
2.2 F
100 nF
Master
ECU
220 pF
ECU Connector
to Single Wire
LIN Bus
47 nF
INH
EN
TxD
1 K
*The NCV7382 is a pin compatible transceiver with INH control.
Figure 9. Application Circuitry
10 F
V
IN
Reset
V
OUT
10 k
100 nF
10 F
Reset
V
IN
10 k
ENABLE

NCV7380DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC TRANSCEIVER LINEAR 8-SOIC
Lifecycle:
New from this manufacturer.
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