AD7910ARMZ Datasheet AD7920AKSZ-500RL7, AD7920BRMZ, AD7910AKSZ-500RL7 | P19-P21

AD7910/AD7920

Rev. C | Page 19 of 24

SERIAL INTERFACE

Figure 23 and Figure 24 show the detailed timing diagram for

serial interfacing to the AD7920 and AD7910, respectively. The

serial clock provides the conversion clock and also controls the

transfer of information from the AD7910/AD7920 during

conversion.

The

signal initiates the data transfer and conversion process.

The falling edge of

puts the track-and-hold into hold mode

and takes the bus out of three-state; the analog input is sampled

at that point. The conversion is also initiated at this point.

For the AD7920, the conversion requires 16 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, track-and-

hold goes back into track on the next SCLK rising edge, as

shown in

Figure 23 at Point B. On the 16th SCLK falling edge,

the SDATA line goes back into three-state. If the rising edge of

occurs before 16 SCLKs have elapsed then the conversion is

terminated and the SDATA line goes back into three-state;

otherwise, SDATA returns to three-state on the 16th SCLK

falling edge, as shown in

Figure 23. Sixteen serial clock cycles

are required to perform the conversion process and to access

data from the AD7920.

For the AD7910, the conversion requires 14 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, track-and-

hold goes back into track on the next SCLK rising edge, as

shown in

Figure 24 at Point B.

If the rising edge of

occurs before 14 SCLKs have elapsed, the

conversion is terminated and the SDATA line goes back into

three-state. If 16 SCLKs are used in the cycle, SDATA returns to

three-state on the 16th SCLK falling edge, as shown in

Figure 24.

going low clocks out the first leading zero to be read in by

the microcontroller or DSP. The remaining data is then clocked

out by subsequent SCLK falling edges beginning with the

second leading zero. Thus, the first falling clock edge on the

serial clock has the first leading zero provided and also clocks

out the second leading zero. The final bit in the data transfer is

valid on the 16th falling edge, having been clocked out on the

previous (15th) falling edge.

In applications with a slower SCLK, it is possible to read in data on

each SCLK rising edge. In this case, the first falling edge of SCLK

clocks out the second leading zero, which could be read in the first

rising edge. However, the first leading zero that was clocked out

when

went low is missed unless it was not read in the first

falling edge. The 15th falling edge of SCLK clocks out the last bit

and it could be read in the 15th rising SCLK edge.

goes low just after the SCLK falling edge has elapsed,

clocks out the first leading zero as before, and it can be read on the

SCLK rising edge. The next SCLK falling edge clocks out the sec-

ond leading zero and it could be read on the following rising edge.

SCLK

DAT

CONVERT

QUIET

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

THREE-STATETHREE-

STATE

4 LEADING ZEROS

15141354321 16

1/THROUGHPUT

02976-023

Figure 23. AD7920 Serial Interface Timing Diagram

SCLK

DAT

CONVERT

QUIET

ZERO ZERO ZERO DB9 DB8 DB0 ZERO ZERO

THREE-STATETHREE-

STATE

4 LEADING ZEROS 2 TRAILING ZEROS

15141354321 16

1/THROUGHPUT

02976-024

Figure 24. AD7910 Serial Interface Timing Diagram

AD7910/AD7920

Rev. C | Page 20 of 24

MICROPROCESSOR INTERFACING

The serial interface on the AD7910/AD7920 allows the parts to

be directly connected to a range of different microprocessors.

This section explains how to interface the AD7910/AD7920

with some of the more common microcontroller and DSP serial

interface protocols.

AD7910/AD7920 TO TMS320C541 INTERFACE

The serial interface on the TMS320C541 uses a continuous serial

clock and frame synchronization signals to synchronize the data

transfer operations with peripheral devices like the

AD7910/AD7920. The

input allows easy interfacing between

the TMS320C541 and the AD7910/AD7920 without any glue logic

required. The serial port of the TMS320C541 is set up to operate in

burst mode (FSM = 1 in the serial port control register, SPC) with

internal serial clock CLKX (MCM = 1 in SPC register) and internal

frame signal (TXM = 1 in the SPC), so both pins are configured as

outputs. For the AD7920, the word length should be set to 16 bits

(FO = 0 in the SPC register). This DSP allows frames with a word

length of 16 bits or 8 bits. Therefore, in the case of the AD7910

where just 14 bits could be required, the FO bit would be set up to

16 bits also. This means that to obtain the conversion result, 16

SCLKs are needed and two trailing zeros are clocked out in the two

last clock cycles.

To summarize, the values in the SPC register are:

FO = 0

FSM = 1

MCM = 1

TXM = 1

The format bit, FO, can be set to 1 to set the word length to

eight bits to implement the power-down mode on the

AD7910/AD7920.

Figure 25 shows the connection diagram. It should be noted

that for signal processing applications, it is imperative that the

frame synchronization signal from the TMS320C541 provides

equidistant sampling.

AD7910/AD7920*

SCLK

SDATA

CLKX

CLKR

FSX

FSR

TMS320C541*

*ADDITIONAL PINS OMITTED FOR CLARITY

02976-025

Figure 25. Interfacing to the TMS320C541

AD7910/AD7920 TO ADSP-218x

The ADSP-218x family of DSPs is interfaced directly to the

AD7910/AD7920 without any glue logic required. The SPORT

control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0, Sets up RFS as an Input

ITFS = 1, Sets up TFS as an Output

SLEN = 1111, 16 Bits for the AD7920

SLEN = 1101, 14 Bits for the AD7910

To implement power-down mode, SLEN should be set to 0111

to issue an 8-bit SCLK burst. The connection diagram is shown

Figure 26. The ADSP-218x has the TFS and RFS of the

SPORT tied together, with TFS set as an output and RFS set as

an input. The DSP operates in alternate framing mode and the

SPORT control register is set up as described. The frame

synchronization signal generated on the TFS is tied to

and,

as with all signal processing applications, equidistant sampling

is necessary. However, in this example, the timer interrupt is

used to control the sampling rate of the ADC and, under certain

conditions, equidistant sampling can not be achieved.

AD7910/AD7920

SCLK

SDATA

SCLK

RFS

TFS

ADSP-218x*

02976-026

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 26. Interfacing to the ADSP-218x

The timer registers are loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and thus the reading

of data. The frequency of the serial clock is set in the SCLKDIV

that is, TX0 = AX0, the state of the SCLK is checked. The DSP

waits until the SCLK has gone high, low, and high before

transmission starts. If the timer and SCLK values are chosen

such that the instruction to transmit occurs on or near the

rising edge of SCLK, the data can be transmitted or it can wait

until the next clock edge.

AD7910/AD7920

Rev. C | Page 21 of 24

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an

SCLK of 2 MHz is obtained and eight master clock periods

elapse for every one SCLK period. If the timer registers are

loaded with the value 803, 100.5 SCLKs occur between

interrupts and subsequently between transmit instructions. This

situation results in nonequidistant sampling as the transmit

instruction is occurring on an SCLK edge. If the number of

SCLKs between interrupts is a whole integer figure of N,

equidistant sampling is implemented by the DSP.

AD7910/AD7920 TO DSP563xx INTERFACE

The diagram in Figure 27 shows how the AD7910/AD7920 can

be connected to the synchronous serial interface (SSI)

(synchronous serial interface) of the DSP563xx family of DSPs

from Motorola. The SSI is operated in synchronous and normal

mode (SYN = 1 and MOD = 0 in Control Register B, CRB) with

internally generated word frame sync for both Tx and Rx (Bit

FSL1 = 0 and Bit FSL0 = 0 in the CRB). Set the word length in

the Control Register A (CRA) to 16 by setting Bits WL2 = 0,

WL1 = 1, and WL0 = 0 for the AD7920. This DSP does not

offer the option for a 14-bit word length, so the AD7910 word

length is set to 16 bits like the AD7920. For the AD7910, the

conversion process uses 16 SCLK cycles, with the last two clock

periods clocking out two trailing zeros to fill the 16-bit word.

To implement the power-down mode on the AD7910/AD7920,

the word length can be changed to eight bits by setting Bits

WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the

CRB register can be set to 1, which means the frame goes low

and a conversion starts. Likewise, by means of Bits SCD2,

SCKD, and SHFD in the CRB register, it is established that Pin

SC2 (the frame sync signal) and SCK in the serial port is

configured as outputs and the MSB is shifted first.

To summarize:

MOD = 0

SYN = 1

WL2, WL1, WL0 Depend on the Word Length

FSL1 = 0, FSL0 = 0

FSP = 1, Negative Frame Sync

SCD2 = 1

SCKD = 1

SHFD = 0

It should be noted that for signal processing applications, it is

imperative that the frame synchronization signal from the

DSP563xx provides equidistant sampling.

AD7910/AD7920*

SDATA

SCLK

DSP563xx*

SCK

SRD

SC2

*ADDITIONAL PINS OMITTED FOR CLARITY

02976-027

Figure 27. Interfacing to the DSP563xx

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

AD7910ARMZ

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Description:

Analog to Digital Converters - ADC 250 kSPS 10-Bit IC

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AD7910ARMZ

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