MC14516BDR2G

MC14516B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbo
l
V
DD
All Types
Unit
Min Typ (Note 6) Max
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Clock to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Carry In
to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Preset or Reset to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Preset or Reset to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 465 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 192 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 125 ns
t
PLH
,
t
PHL
5.0
10
15
315
130
100
630
260
200
ns
t
PLH
,
t
PHL
5.0
10
15
315
130
100
630
260
200
ns
t
PLH
,
t
PHL
5.0
10
15
180
80
60
360
160
120
ns
t
PLH
,
t
PHL
5.0
10
15
315
130
100
630
360
200
ns
t
PLH
,
t
PHL
5.0
10
15
550
225
150
1100
450
300
ns
Reset Pulse Width t
w
5.0
10
15
380
200
160
190
100
80
ns
Clock Pulse Width t
WH
5.0
10
15
350
170
140
200
100
75
ns
Clock Pulse Frequency f
cl
5.0
10
15
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Preset or Reset Removal Time
The Preset or Reset signal must be low prior to a
positive−going transition of the clock.
t
rem
5.0
10
15
650
230
180
325
115
90
ns
Clock Rise and Fall Time t
TLH
,
t
THL
5.0
10
15
15
5
4
ms
Setup Time
Carry In
to Clock
t
su
5.0
10
15
260
120
100
130
60
50
ns
Hold Time
Clock to Carry In
t
h
5.0
10
15
0
20
20
– 60
– 20
0
ns
Setup Time
Up/Down to Clock
t
su
5.0
10
15
500
200
150
250
100
75
ns
Hold Time
Clock to Up/Down
t
h
5.0
10
15
– 70
– 10
0
– 160
– 60
– 40
ns
Setup Time
Pn to PE
t
su
5.0
10
15
– 40
– 30
– 25
– 120
– 70
– 50
ns
Hold Time
PE to Pn
t
h
5.0
10
15
480
420
420
240
210
210
ns
Preset Enable Pulse Width t
WH
5.0
10
15
200
100
80
100
50
40
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
MC14516B
http://onsemi.com
5
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR
C
L
C
L
C
L
C
L
V
DD
VARIABLE
WIDTH
V
DD
V
SS
CLOCK
I
D
0.01 mF
CERAMIC
20 ns
20 ns
10%
50%
90%
500 pF
Q0
Q1
Q2
Q3
CARRY
OUT
PE
CARRY IN
R
UP/DOWN
CLOCK
P0
P1
P2
P3
C
L
LOGIC DIAGRAM
PE
C
T
Q
Q
P
PE
C
T
Q
Q
P
PE
C
T
Q
Q
P
PE
C
T
Q
Q
P
Q2
14
P2
13
Q1
11
P3
3
Q3
2
P0
4
Q0
6
P1
12
CARRY OUT
CLOCK
PRESET
ENABLE
RESET
CARRY IN
UP/DOWN
9
1
15
7
5
10
MC14516B
http://onsemi.com
6
TOGGLE FLIP−FLOP
PE
C
T
Q
Q
P
PARALLEL IN
FLIP−FLOP FUNCTIONAL TRUTH TABLE
Preset
Enable
Clock T Q
n+1
1 X X Parallel In
0 0 Q
n
0 1 Q
n
0 X Q
n
X = Don’t Care
Figure 2. Switching Time Waveforms
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
OL
V
OH
RESET
PRESET ENABLE
CARRY IN OR
UP/DOWN
CLOCK
Q
0
OR CARRY OUT
t
rem
t
su
t
rem
t
h
t
TLH
t
PLH
t
PHL
t
PLH
t
THL
50%
50%
90%
10%
50%
90%
10%
CARRY OUT
ONLY
t
w(H)
t
w(H)
t
w
1
f
cl
PIN DESCRIPTIONS
INPUTS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In
, (Pin 5) This active−low input is used when
Cascading stages. Carry In
is usually connected to Carry Out
of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) Binary data is incremented or
decremented, depending on the direction of count, on the
positive transition of this input.
OUTPUTS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2)
Binary data is present on these outputs with Q0
corresponding to the least significant bit.
Carry Out,
(Pin 7) Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
CONTROLS
PE, Preset Enable, (Pin 1) Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) Asynchronously resets the Q out−
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) Controls the direction of count,
high for up count, low for down count.
SUPPLY PINS
V
SS
, Negative Supply Voltage, (Pin 8) This pin is
usually connected to ground.
V
DD
, Positive Supply Voltage, (Pin 16) This pin is
connected to a positive supply voltage ranging from 3.0 V
to 18 V.

MC14516BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 3-18V Binary Up/Down
Lifecycle:
New from this manufacturer.
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