9ZXL1930BKLFT Datasheet 9ZXL1930BKLFT, 9ZXL1930BKLF | P1-P3

DATASHEET

19-OUTPUT DB1900Z LOW-POWER DERIVATIVE

9ZXL1930

IDT®

19-OUTPUT DB1900Z LOW-POWER DERIVATIVE 1

9ZXL1930 REV D 112015

Description

The 9ZXL1930 is a low power version of the Intel DB1900Z

Differential Buffer utilizing Low-Power HCSL (LP-HCSL)

outputs to reduce power consumption more than 50% from

the original IDT9ZX21901. It is suitable for PCI-Express

Gen1/2/3 or QPI/UPI applications, and uses a fixed external

feedback to maintain low drift for demanding QPI/UPI

applications.

Recommended Application

Buffer for Romley, Grantley and Purley Servers

Key Specifications

• Cycle-to-cycle jitter: < 50ps

• Output-to-output skew: <85ps

• Input-to-output delay: Fixed at 0 ps

• Input-to-output delay variation: <50ps

• Phase jitter: PCIe Gen3 < 1ps rms

• Phase jitter: QPI/UPI 9.6GB/s < 0.2ps rms

Features/Benefits

• Fixed feedback path; 0ps input-to-output delay

• 9 Selectable SMBus addresses; Multiple devices can

share same SMBus segment

• Separate VDDIO for outputs; allows maximum power

savings

• PLL or bypass mode; PLL can dejitter incoming clock

• Selectable PLL BW; minimizes jitter peaking in

downstream PLL's

• Spread spectrum compatible; tracks spreading input

clock for EMI reduction

• SMBus Interface; unused outputs can be disabled

• 100MHz & 133.33MHz PLL mode; Legacy QPI/UPI

support

• Differential outputs are Low/Low in power down;

Maximum power savings

Output Features

• 19 - LP-HCSL Differential Output Pairs

Block Diagram

Logic

HIBW_BYPM_LOBW#

SMBDAT

SMBCLK

CKPWRGD/PD#

SMB_A0_tri

SMB_A1_tri

100M_133M#

Z-PLL

(SS Compatible)

FBOUT_NC

DIF_IN

DIF_IN#

DIF18

DIF0

9ZXL1930

19-OUTPUT DB1900Z LOW-POWER DERIVATIVE

IDT®

19-OUTPUT DB1900Z LOW-POWER DERIVATIVE 2

9ZXL1930 REV D 112015

Pin Configuration

Power Management Table

Power Connections

Functionality at Power-up (PLL mode)

PLL Operating Mode Table

Tri-Level Input Thresholds

DIF_18#

DIF_18

GND

VDDIO

DIF_17#

DIF_17

DIF_16#

DIF_16

VDD

GND

DIF_15#

DIF_15

DIF_14#

DIF_14

GND

VDD IO

DIF_13#

DIF_13

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

VDDA 1 54

DIF_12#

GNDA 2 53

DIF_12

100M_133M# 3 52

VDDIO

HIBW_BYPM_LOBW# 4 51

GN D

CKPWRGD_PD# 5 50

DIF_11#

GND 6 49

DIF_11

VDDR 7 48

DIF_10#

DIF_IN 8 47

DIF_10

DIF_IN# 9 46

GN D

SMB_ A0_tri 10 45

VDD

SMBDAT 11 44

DIF_9#

SMBCLK 12 43

DIF_9

SMB_ A1_tri 13 42

DIF_8#

FBOUT_NC# 14 41

DIF_8

FBOUT_NC 15 40

VDDIO

GND 16 39

GN D

DIF_0 17 38

DIF_7#

DIF_0# 18 37

DIF_7

19 20 21 22 23 24 25 26 27 28 29 30 31 32 3 3 34 35 36

DIF_1

DIF_1#

VDDIO

GND

DIF_2

DIF_2#

DIF_3

DIF_3#

GND

VDD

DIF_4

DIF_4#

DIF_5

DIF_5#

VDDIO

GND

DIF_6

DIF_6#

9ZXL1930

Control Bits

CKPWRGD_PD#

DIF_IN/

DIF_IN#

SMBus

EN bit

DIF_x/

DIF_x#

FBOUT_NC/

FB_OUT_NC#

0 X X Low/Low Low/Low OFF

0 Low /Low Running ON

1 Running Running ON

Inputs

PLL State

1 Running

Outputs

VDD VDDIO GND

1 2 Analog PLL

7 6 Analog Input

28, 45, 64

21, 33, 40,

52, 57, 69

16, 22, 27, 34,

39, 46, 51, 58,

63, 70

D IF clocks

Pin Numbe

Description

100M_133M#

DIF_IN

(MHz)

DIFx

(MHz)

1 100.00 DIF_IN

0 133.33 DIF_IN

HiBW_BypM_LoBW# Byte0, bit (7:6)

Low ( PLL Low BW) 00

Mid (Bypass) 01

High (PLL High BW) 11

NOTE: PLL is off in Bypass mode

Level Voltage

Low <0.8V

Mid 1.2<Vin<1.8V

High

Vin > 2.2V

9ZXL1930

19-OUTPUT DB1900Z LOW-POWER DERIVATIVE

IDT®

19-OUTPUT DB1900Z LOW-POWER DERIVATIVE 3

9ZXL1930 REV D 112015

Pin Descriptions

PIN # PIN NAME PIN TYPE DESCRIPTION

1 VDDA PWR 3.3V power for the PLL core.

2 GNDA PWR Ground

i n for the PLL core.

3100M_133M# IN

3.3V Input to select operating frequency

See Functionalit

Table for Definition

4 HIBW_BYPM_LOBW# IN

Trilevel input to select High BW, Bypass or Low BW mode.

See PLL Operating Mode Table for Details.

5 CKPWRGD_PD# IN

Notifies device to sample latched inputs and start up on first high assertion, or exit

Power Down Mode on subsequent assertions. Low enters Power Down Mode.

6 GND PWR Ground

in.

7 VDDR PWR

3.3V power for differential input clock (receiver). This VDD should be treated as an

analog power rail and filtered appropriately.

8 DIF_IN IN 0.7 V Differential TRUE input

9 DIF_IN# IN 0.7 V Differential Complementary Input

10 SMB_A0_tri IN

SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1

to decode 1 of 9 SMBus Addresses.

11 SMBDAT I/O Data

in of SMBUS circuitr

, 5V tolerant

12 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant

13 SMB_A1_tri IN

SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0

to decode 1 of 9 SMBus Addresses.

14 FBOUT_NC# OUT

Complementary half of differential feedback output. This pin should NOT be connected

to anything outside the chip. It exists to provide delay path matching to get 0

ation de la

15 FBOUT_NC OUT

True half of differential feedback output. This pin should NOT be connected to anything

outside the chip. It exists to provide delay path matching to get 0 propagation delay.

16 GND PWR Ground pin.

17 DIF_0 OUT 0.7V differential true clock output

18 DIF_0# OUT 0.7V differential Complementary clock output

19 DIF_1 OUT 0.7V differential true clock out

20 DIF_1# OUT 0.7V differential Com

lementar

clock out

21 VDDIO PWR Power supply for differential outputs

22 GND PWR Ground pin.

23 DIF_2 OUT 0.7V differential true clock output

24 DIF_2# OUT 0.7V differential Complementary clock output

25 DIF_3 OUT 0.7V differential true clock out

26 DIF_3# OUT 0.7V differential Com

lementar

clock out

27 GND PWR Ground

in.

28 VDD PWR Power supply, nominal 3.3V

29 DIF_4 OUT 0.7V differential true clock output

30 DIF_4# OUT 0.7V differential Complementary clock output

31 DIF_5 OUT 0.7V differential true clock out

32 DIF_5# OUT 0.7V differential Com

lementar

clock out

33 VDDIO PWR Pow er su

for differential out

uts

34 GND PWR Ground pin.

35 DIF_6 OUT 0.7V differential true clock output

36 DIF_6# OUT 0.7V differential Complementary clock output

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

9ZXL1930BKLFT

Mfr. #:

Buy 9ZXL1930BKLFT

Manufacturer:

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Description:

Clock Buffer HIGH PERF. ZDB

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9ZXL1930BKLFT

9ZXL1930BKLFT

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