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NCP1250BP65G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
NCP1250
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13
APPLICATION INFORMATION
Introduction
The NCP1250 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count and cost effectiveness are
the key parameters, particularly in low−cost ac−dc adapters,
open−frame power supplies etc. Capitalizing on the
NCP120X series success, the NCP1250 packs all the
necessary components normally needed in today modern
power supply designs, bringing several enhancements such
as a non−dissipative OPP.
• Current−mode operation with internal ramp
compensation: Implementing peak current mode
control at a fixed 65 kHz or 100 kHz, the NCP1250
offers an internal ramp compensation signal that can
easily by summed with the sensed current. Sub
harmonic oscillations are eliminated via the inclusion of
a single resistor in series with the current−sense
information.
• Internal OPP: By routing a portion of the negative
voltage present during the on−time on the auxiliary
winding to the dedicated OPP pin, the user has a simple
and non−dissipative means to alter the maximum peak
current setpoint as the bulk voltage increases. If the pin
is grounded, no OPP compensation occurs. If the pin
receives a negative voltage down to –250 mV, then a
peak current reduction down to 31.3% typical can be
achieved. For an improved performance, the maximum
voltage excursion on the sense resistor is limited to
0.8 V.
• Low startup current: Achieving a low no−load
standby power always represents a difficult exercise
when the controller draws a significant amount of
current during start−up. Due to its proprietary
architecture, the NCP1250 is guaranteed to draw less
than 15 mA typical, easing the design of low standby
power adapters.
• EMI jittering: An internal low−frequency modulation
signal varies the pace at which the oscillator frequency
is modulated. This helps by spreading out energy in
conducted noise analysis. To improve the EMI
signature at low power levels, the jittering remains
active in frequency foldback mode.
• Frequency foldback capability: A continuous flow of
pulses is not compatible with no−load/light−load
standby power requirements. To excel in this domain,
the controller observes the feedback pin and when it
reaches a level of 1.5 V, the oscillator then starts to
reduce its switching frequency as the feedback level
continues to decrease. When the feedback pin reaches
1.05 V, the peak current setpoint is internally frozen and
the frequency continues to decrease. It can go down to
26 kHz (typical) reached for a feedback level of
roughly 350 mV. At this point, if the power continues to
drop, the controller enters classical skip−cycle mode.
• Internal soft−start: A soft−start precludes the main
power switch from being stressed upon start−up. In this
controller, the soft−start is internally fixed to 4 ms. The
soft−start is activated when a new startup sequence
occurs or during an auto−recovery hiccup.
• OVP input: The NCP1250 includes a latch input Pin
that can be used to sense an overvoltage condition on
the adapter. If this pin is brought higher than the
internal reference voltage V
latch
, then the circuit
permanently latches off. The V
CC
pin is pulled down to
a fixed level, keeping the controller latched. The latch
reset occurs when the user disconnects the adapter from
the mains and lets the V
CC
falls below the V
CC
reset.
• Short−circuit protection: Short−circuit and especially
over−load protections are difficult to implement for
transformers with high leakage inductance between
auxiliary and power windings (the aux winding level
does not properly collapse in presence of an output
short). Here, every time the internal 0.8 V maximum
peak current limit is activated (or less when OPP is
used), an error flag is asserted and a time period starts,
thanks to an internal timer. If the timer reaches
completion while the error flag is still present, the
controller stops the pulses and goes into a latch−off
phase, operating in a low−frequency burst−mode. When
the fault is cleared, the SMPS resumes operation.
Please note that some versions offer an auto−recovery
mode as described and some latch off in case of a short
circuit.
Start−up Sequence
The NCP1250 start−up voltage is made purposely high to
permit a large energy storage in a small V
CC
capacitor value.
This helps to operate with a small start−up current which,
together with a small V
CC
capacitor, will not hamper the
start−up time. To further reduce the standby power, the
start−up current of the controller is extremely low, below
15 mA maximum. The start−up resistor can therefore be
connected to the bulk capacitor or directly to the mains input
voltage to further reduce the power dissipation.
NCP1250
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14
11
1
R1
200k
10
R2
200k
3
R3
200k
5
D1
1N4007
12
D2
1N4007
Cbulk
22uF
C1
4.7uF
D3
1N4007
D4
1N4007
input
mains
42
D5
1N4935
C3
47uF
D6
1N4148
VCC
aux.
Figure 39. The Startup Resistor Can Be Connected to the Input Mains for Further Power Dissipation Reduction
The first step starts with the calculation of the V
CC
capacitor which will supply the controller when it operates
until the auxiliary winding takes over. Experience shows
that this time t
1
can be between 5 ms and 20 ms. If we
consider we need at least an energy reservoir for a t
1
time of
10 ms, the V
CC
capacitor must be larger than:
CV
CC
w
I
CC
t
1
VCC
on
* VCC
min
w
3m 10m
9
w 3.3 mF
(eq. 1)
Let us select a 4.7 mF capacitor at first and experiments in
the laboratory will let us know if we were too optimistic for
the time t
1
. The V
CC
capacitor being known, we can now
evaluate the charging current we need to bring the V
CC
voltage from 0 to the VCC
on
of the IC, 18 V typical. This
current has to be selected to ensure a start−up at the lowest
mains (85 V rms) to be less than 3 s (2.5 s for design margin):
I
charge
w
VCC
on
C
VCC
2.5
w
18 4.7m
2.5
w 34 mA
(eq. 2)
If we account for the 15 mA that will flow inside the
controller, then the total charging current delivered by the
start−up resistor must be 49 mA. If we connect the start−up
network to the mains (half−wave connection then), we know
that the average current flowing into this start−up resistor
will be the smallest when V
CC
reaches the VCC
on
of the
controller:
I
CVCC,min
+
V
ac,rms
2
Ǹ
p
* VCC
on
R
start*up
(eq. 3)
To make sure this current is always greater than 49 mA,
then the minimum value for R
start−up
can be extracted:
R
start*up
v
V
ac,rms
2
Ǹ
p
* VCC
on
I
CVCC,min
v
85 1.414
p
* 18
49m
v 413.5 k
W
(eq. 4)
This calculation is purely theoretical, and assumes a
constant charging current. In reality, the take over time can
be shorter (or longer!) and it can lead to a reduction of the
V
CC
capacitor. Hence, a decrease in charging current and an
increase of the start−up resistor, thus reducing the standby
power. Laboratory experiments on the prototype are thus
mandatory to fine tune the converter. If we chose the 413 kW
resistor as suggested by Equation 4, the dissipated power at
high line amounts to:
P
Rstart*up
+
V
ac,peak
2
4R
start*up
+
ǒ
230 2
Ǹ
Ǔ
2
4 413k
(eq. 5)
+
230
2
0.827Meg
+ 64 mW
Now that the first V
CC
capacitor has been selected, we
must ensure that the self−supply does not disappear when in
no−load conditions. In this mode, the skip−cycle can be so
deep that refreshing pulses are likely to be widely spaced,
inducing a large ripple on the V
CC
capacitor. If this ripple is
too large, chances exist to touch the VCC
min
and reset the
controller into a new start−up sequence. A solution is to
grow this capacitor but it will obviously be detrimental to the
start−up time. The option offered in Figure 39 elegantly
solves this potential issue by adding an extra capacitor on the
auxiliary winding. However, this component is separated
from the V
CC
pin via a simple diode. You therefore have the
ability to grow this capacitor as you need to ensure the
self−supply of the controller without jeopardizing the
start−up time and standby power. A capacitor ranging from
22 to 47 mF is the typical value for this device.
One note on the start-up current. If reducing it helps to
improve the standby power, its value cannot fall below a
certain level at the minimum input voltage. Failure to inject
NCP1250
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15
enough current (30 mA) at low line will turn a converter in
fault into an auto-recovery mode since the SCR won’t
remain latched. To build a sufficient design margin, we
recommend to keep at least 60 mA flowing at the lowest input
line (80 V rms for 85 V minimum for instance). An excellent
solution is to actually combine X2 discharge and start-up
networks as proposed in Figure 13 of application note
AND8488/D.
Internal Over Power Protection
There are several known ways to implement Over Power
Protection (OPP), all suffering from particular problems.
These problems range from the added consumption burden
on the converter or the skip−cycle disturbance brought by
the current−sense offset. A way to reduce the power
capability at high line is to capitalize on the negative voltage
swing present on the auxiliary diode anode. During the
power switch on−time, this point dips to −NV
in
, N being the
turns ratio between the primary winding and the auxiliary
winding. The negative plateau observed on Figure 41 will
have an amplitude dependant on the input voltage. The idea
implemented in this chip is to sum a portion of this negative
swing with the 0.8 V internal reference level. For instance,
if the voltage swings down to −150 mV during the on time,
then the internal peak current set point will be fixed to 0.8 −
0.150 = 650 mV. The adopted principle appears in Figure 41
and shows how the final peak current set point is
constructed.
1
v(24)
464u 472u 480u 488u 496u
time (s)
−40.0
−20.0
0
20.0
40.0
v(24) (V)
1
on−time
1
v(24)
−40.0
−20.0
0
20.0
40.0
1
off−time
Figure 40. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time
N
1
(V
out
+V
f
)
−N
2
V
bulk
Let’s assume we need to reduce the peak current from
2.5 A at low line, to 2 A at high line. This corresponds to a
20% reduction or a set point voltage of 640 mV. To reach this
level, then the negative voltage developed on the OPP pin
must reach:
V
OPP
+ 640m * 800m + −160 mV
(eq. 6)
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NCP1250BP65G

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers ACDC SWITCH OCP AUTO
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