NCP1250
www.onsemi.com
5
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
= −40°C to +125°C, Max T
J
= 150°C, V
CC
= 12 V unless otherwise noted)
Symbol Rating Min Typ Max Unit
SUPPLY SECTION − (For the best efficiency performance, we recommend a V
CC
below 20 V)
VCC
ON
V
CC
increasing level at which driving pulses are authorized 16 18 20 V
VCC
(min)
V
CC
decreasing level at which driving pulses are stopped 8.2 8.8 9.4 V
VCC
HYST
Hysteresis VCC
ON
− VCC
(min)
6.0 V
V
ZENER
Clamped V
CC
when latched off / burst mode activation @ I
CC
= 500 mA
7.0 V
ICC1 Start−up current 15
mA
ICC2
Internal IC consumption with I
FB
= 50 mA, F
SW
= 65 kHz and C
L
= 0 nF
1.4 2.2 mA
ICC3
Internal IC consumption with I
FB
= 50 mA, F
SW
= 65 kHz and C
L
= 1 nF
2.1 3.0 mA
ICC2
Internal IC consumption with I
FB
= 50 mA, F
SW
= 100 kHz and C
L
= 0 nF
1.7 2.5 mA
ICC3
Internal IC consumption with I
FB
= 50 mA, F
SW
= 100 kHz and C
L
= 1 nF
3.1 4.0 mA
ICC
LATCH
Current flowing into V
CC
pin that keeps the controller latched (Note 4)
T
J
= −40°C to +125°C
T
J
= 0°C to +125°C
40
32
mA
ICCstby Internal IC consumption while in skip cycle (V
CC
= 12 V, driving a typical 6 A/600 V MOS-
FET)
550
mA
R
lim
Current−limit resistor in series with the latch SCR 4.0
kW
DRIVE OUTPUT
T
r
Output voltage rise−time @ C
L
= 1 nF, 10−90% of output signal 40 ns
T
f
Output voltage fall−time @ C
L
= 1 nF, 10−90% of output signal 30 ns
R
OH
Source resistance 13
W
R
OL
Sink resistance 6.0
W
I
source
Peak source current, V
GS
= 0 V – (Note 5) 300 mA
I
sink
Peak sink current, V
GS
= 12 V – (Note 5) 500 mA
V
DRVlow
DRV pin level at V
CC
close to VCC
(min)
with a 33 kW resistor to GND
8.0 V
V
DRVhigh
DRV pin level at V
CC
= 28 V – DRV unloaded 10 12 14 V
CURRENT COMPARATOR
I
IB
Input Bias Current @ 0.8 V input level on CS Pin 0.02
mA
V
Limit1
Maximum internal current setpoint – T
J
= 25°C – OPP/Latch Pin grounded 0.744 0.8 0.856 V
V
Limit2
Maximum internal current setpoint – T
J
= −40°C to 125°C – OPP/Latch Pin grounded 0.72 0.8 0.88 V
V
fold
Default internal voltage set point for frequency foldback trip point – 45% of V
limit
357 mV
V
freeze
Internal peak current setpoint freeze ([31% of V
limit
) 250 mV
T
DEL
Propagation delay from current detection to gate off−state 100 150 ns
T
LEB
Leading Edge Blanking Duration 300 ns
TSS Internal soft−start duration activated upon startup, auto−recovery 4.0 ms
IOPPo Setpoint decrease for the OPP/Latch pin biased to –250 mV – (Note 6) 31.3 %
IOOPv Voltage setpoint for the OPP/Latch pin biased to −250 mV – (Note 6), T
J
= 25°C 0.51 0.55 0.60 V
IOOPv Voltage setpoint for the OPP/Latch pin biased to −250 mV – (Note 6), T
J
= −40°C to
125°C
0.50 0.55 0.62 V
IOPPs Setpoint decrease for the OPP/Latch pin grounded 0 %
INTERNAL OSCILLATOR
f
OSC
Oscillation frequency (65 kHz version) 61 65 71 kHz
f
OSC
Oscillation frequency (100 kHz version) 92 100 108 kHz
