ISL36111DRZ-T7

ISL36111
7
FN6974.2
July 19, 2012
Application Information
Typical application schematic for ISL36111 is shown in Figure 8.
PCB Layout Considerations
Because of the high speed of the ISL36111 signals, careful PCB
layout is critical to maximize performance. The following
guidelines should be adhered to as closely as possible:
All high speed differential pair traces should have a
characteristic impedance of 50Ω with respect to ground plane
and 100Ω with respect to each other.
Avoid using vias for high speed traces as this will create
discontinuity in the traces characteristic impedance.
Input and output traces need to have DC blocking capacitors
(100nF). Capacitors should be placed as close to the chip as
possible.
For each differential pair, the positive trace and the negative
trace need to be of same length in order to avoid intra-pair
skew. Serpentine technique may be used to match trace
lengths.
Maintain a constant solid ground plane underneath the high-
speed differential traces
•Each V
DD
pin should be connected to 1.2V and also bypassed
to ground through a 47nF and a 100pF capacitor in parallel.
Minimize the trace length and avoid vias between the V
DD
pin
and the bypass capacitors in order to maximize the power
supply noise rejection.
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FIGURE 8. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL36111
NOTES:
14. See “Control Pin Boost Setting” on page 5 for information on how to connect the CP pins
15. See “Detection Thereshold (DT) Pin Functionality” on page 6 for details on DT pin operation.
16. Although the filtering network is shown only for one V
DD
pin for simplicity, all the V
DD
pins need to be connected in this way.
DT
CPA
CPB
LOSB (output)
1.2V
1.2V
1.2V
47nF47nF
ISL36111
IN_P
2
IN_N
3
DT
15
VDD
1
VDD
9
VDD
12
OUT_N
10
OUT_P
11
NC
14
LOSB
4
GND
16
GND
5
CPA
6
CPB
7
GND
8
GND
13
100nF100nF
100nF100nF
100pF
100pF
100nF100nF
100nF100nF
INPUT SIGNAL
OUTPUT SIGNAL
ISL36111
8
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6974.2
July 19, 2012
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products
for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL36111
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
July 12, 2012 FN6974.2 On page 1, Column 1, changed last paragraph from:
"Operating on a single 1.2V power supply, the ISL36111 enables channel throughputs of 10Gb/s to 11.1Gb/s
while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125 and 2.5Gb/s."
to:
"Operating on a single 1.2V power supply, the ISL36111 enables channel throughputs of 10Gb/s to 11.1Gb/s
while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125, 2.5 and 1 Gb/s."
In “Electrical Specifications” on page 3 , changed Min Entry for “Bit Rate” from: "2.5Gb/s" to: "1Gb/s"
Added Note 14 to MIN and MAX columns of spec tables.
October 27, 2010 FN6974.1 1. Added “Application Information” on page 7, Figure 8 on page 7, and “PCB Layout Considerations” on page 7
2. Corrected “Pin Descriptions” on page 2 for VDD pin from "and 10nF decoupling capacitors.." to “and 47nF
decoupling capacitors.."
3. Corrected “Pin Descriptions” on page 2 for CP[A,B] pin from "Pins are read as a 3-digit number.." to "Pins are
read as a 2-digit number.."
November 19, 2009 FN6974.0 Initial Release to web
ISL36111
9
FN6974.2
July 19, 2012
Package Outline Drawing
L16.3x3B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
BOTTOM VIEW
SIDE VIEW
9
( 2. 80 TYP )
( 1. 70 )
(4X)
0.15
( 12X 0 . 5 )
( 16X 0 . 60)
( 16X 0 . 23 )
0 . 90 ± 0.1
INDEX AREA
PIN 1
6
A
3.00
B
3.00
12
4
4
5
8
16X 0.40 ± 0.10
5
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
BCMA0.10
C
- 0.05
BASE PLANE
0.10
C
SEE DETAIL "X"
C
0.08
SEATING PLANE
+ 0.07
16X 0.23
16
13
12X
1.5
4X
0.50
1
6
PIN #1 INDEX AREA
1 .70
+ 0.10
- 0.15

ISL36111DRZ-T7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Equalizers ISL36111DRZ-EVALZ EVAL BRD RHS COMPLIA
Lifecycle:
New from this manufacturer.
Delivery:
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