AT88SA102S-TH-T Datasheet AT88SA102S-TH-T, AT88SA102S-SH-T, AT88SA102S-TSU-T | P10-P12

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5.1.1 Command Timing

After a command flag is transmitted, a command block should be sent to the chip. During parsing of the parameters and

subsequent execution of a properly received command, the chip will be busy and not respond to transitions on the signal pin.

The delays for these operations are listed in the table below:

Table 5-2. Command Timing (Guaranteed by design; not tested)

Parameter Symbol Max Unit Notes

Parsing Delay

PARSE

100

µs

Delay to check CRC and parse opcode and parameters before an

error indication will be available

MacDelay

EXEC_MAC

30 ms Delay to execute MAC command

MemoryDelay

EXEC_READ

3 ms Delay to execute Read command

Fuse Delay

EXEC_FUSE

700

µs

Delay to execute BurnFuse command

See Section 6.3 for more details.

SecureDelay

EXEC_SECURE

36 ms Max delay to execute BurnSecure command

See Section 6.5 for more details.

PersonalizeDelay

PERSON

13 ms Delay to execute GenPersonalizationKey

In this document, t

EXEC

is used as shorthand for the delay corresponding to whatever command has been sent to the chip.

5.1.2 Transmit Flag

The Transmit flag is used to turn around the signal so that the AT88SA102S can send data back to the system, depending on

its current state. The bytes that the AT88SA102S returns to the system depend on its current state as follows:

Table 5-3. Return Codes

State Description Error/Status Description

After Wake, but prior to

first command

0x11 Indication that a proper Wake token has been received by Atmel

AT88SA102S

After successful command

execution

– Return bytes per “Output Parameters” in Section 6, Commands. In some

cases this is a single byte with a value of 0x00 indicating success. The

Transmit flag can be resent to the AT88SA102S repeatedly if a re-read of

the output is necessary.

Execution error 0x0F Command was properly received but could not be executed by the

AT88SA102S. Changes in the AT88SA102S state or the value of the

command bits must happen before it is re-attempted.

After CRC or other

communications error

0xFF

Command was not properly received by the AT88SA102S and should be

re-issued by the system. No attempt was made to execute the command

The AT88SA102S always transmits complete blocks to the system, so in the above table the status/error bytes result in

4-bytes going to the system – count, status/error, CRC x 2.

After receipt of a command block, AT88SA102S will parse the command for errors, a process which takes t

PARSE

(See Section

5.1.1). After this interval the system can send a transmit token to AT88SA102S – if there was an error, then AT88SA102S will

respond with an error code. If there is no error, then AT88SA102S internally transitions automatically from t

PARSE

to t

EXEC

and

will not respond to any transmit tokens until both delays are complete.

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5.1.3 Sleep Flag

The sleep flag is used to transition AT88SA102S to the low power state, which causes a complete reset of the AT88SA102S

internal command engine and input/output buffer. It can be sent to AT88SA102S at any time when AT88SA102S will accept a

flag.

To achieve the specified I

SLEEP

, Atmel recommends that the input signal be brought below V

when the chip is asleep. To

achieve I

SLEEP

if the sleep state of the input pin is high, the voltage on the input signal should be within 0.3 V of V

to avoid

additional leakage on the input circuit of the chip.

The system must calculate the total time required for all commands to be sent to AT88SA102S during a single session,

including any inter-bit/byte delays. If this total time exceeds t

WATCHDOG

then the system must issue a partial set of commands,

then a Sleep flag, then a Wake token, and finally after the Wake delay the remaining commands.

5.1.4 Pause State

The pause state is entered via the PauseLong command and can be exited only when the watchdog timer has expired and the

chip transitions to a sleep state. When in the pause state, the chip ignores all transitions on the signal pin but does not enter a

low power consumption mode.

The pause state provides a mechanism for multiple AT88SA102S chips on the same wire to be selected and to exchange data

with the host microprocessor. The PauseLong command includes an optional address field which is compared to the values in

Fuses 84-87. If the two matches, then the chip enter the pause state, otherwise it continues to monitor the bus for subsequent

commands. The host would selectively put all but one AT88SA102S’ in the pause state before executing the MAC command

on the active chip. After the end of the watchdog interval all the chips will have entered the sleep state and the selection

process can be started with a Wake token (which will then be honored by all chips) and selection of a subsequent chip.

5.2 IO Blocks

Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way:

The general IO flow for the MAC command is as follows:

1. System sends Wake token

2. System sends Transmit flag

3. Receive 0x11 value from the AT88SA102S to verify proper wakeup synchronization

4. System sends command flag

5. System sends complete command block

6. System waits t

PARSE

for the AT88SA102S to check for command formation errors

7. System sends Transmit flag. If command format is OK, the AT88SA102S ignores this flag because the computation

engine is busy. If there was an error, the AT88SA102S responds with an error code

8. System waits t

EXEC

, see Section 5.1.1

9. System sends transmit flag

10. Receive output block from the AT88SA102S, system checks CRC

11. If CRC from the AT88SA102S is incorrect, indicating a transmission error, system resends transmit flag

12. System sends sleep flag to the AT88SA102S

All commands other than MAC have a short execution delay. In these cases, the system should omit steps six, seven, and

eight and replace this with a wait of duration t

PARSE

+ t

EXEC

5.3 Synchronization

Because the communications protocol is half duplex, there is the possibility that the system and AT88SA102S will fall out of

synchronization with each other. In order to speed recovery, AT88SA102S implements a timeout that forces the chip to sleep.

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5.3.1 IO Timeout

After a leading transition for any data token has been received, the AT88SA102S will expect the remaining bits of the token to

be properly received by the chip within the t

TIMEOUT

interval. Failure to send enough bits or the transmission of an illegal token

(a low pulse exceeding t

ZLO

) will cause the chip to enter the sleep state after the t

TIMEOUT

interval.

The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the

IO Timeout circuitry is enabled until the last expected data bit is received.

Note: The timeout counter is reset after every legal token, so the total time to transmit the command may exceed the

TIMEOUT

interval while the time between bits may not.

In order to limit the active current if AT88SA102S is inadvertently awakened, the IO timeout circuitry is also enabled when

AT88SA102S receives a wake-up. If the first token does not come within the t

TIMEOUT

interval, then AT88SA102S will go back

to the sleep mode without performing any operations.

The IO timeout circuitry is disabled when the chip is busy executing a command.

5.3.2 Synchronization Procedures

When the system and the AT88SA102S fall out of synchronization, the system will ultimately end up sending a transmit flag

which will not generate a response from AT88SA102S. The system should implement its own timeout which waits for t

TIMEOUT

during which time AT88SA102S should go to sleep automatically. At this point, the system should send a Wake token and

after t

WLO

+ t

WHI

, a transmit token. The 0x11 status indicates that the resynchronization was successful.

It may be possible that the system does not get the 0x11 code from AT88SA102S for one of the following reasons:

1. The system did not wait a full t

TIMEOUT

delay with the IO signal idle in which case AT88SA102S may have interpreted

the Wake token and transmit flag as data bits. Recommended resolution is to wait twice the t

TIMEOUT

delay and re-issue

the Wake token.

2. AT88SA102S went into the sleep mode for some reason while the system was transmitting data. In this case,

AT88SA102S will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted bits

during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag,

though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a

correct CRC. Recommended resolution is to wait the t

TIMEOUT

delay and re-issue the Wake token.

3. There is some internal error condition within AT88SA102S which will be automatically reset after a t

WATCHDOG

interval,

see Section 5.4. There is no way to externally reset AT88SA102S – the system should leave the IO pin idle for this

interval and issue the Wake token.

5.4 Watchdog Failsafe

After the Wake token has been received by AT88SA102S, a watchdog counter is started within the chip. After t

WATCHDOG

, the

chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO

transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again.

This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state

machines of AT88SA102S including any IO synchronization issue, power consumption will fall to the low sleep level

automatically.

5.5 Byte and Bit Ordering

AT88SA102S is a little-endian chip:

• All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order

received

• Data is transferred to/from the AT88SA102S least significant bit first on the bus

• In this document, the most significant bit and/or byte appears towards the left hand side of the page

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

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