IDT
®
Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
11
Datasheet
AC Electrical Characteristics - Low Power Differential Outputs, Commercial Temperature Range
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Rising Edge Slew Rate tSLR Averaging on 2.5 3.7 4 V/ns 2, 3
Falling Edge Slew Rate tFLR Averaging on 2.5 3.7 4 V/ns 2, 3
Slew Rate Variation tSLVAR Averaging on 3.6 20 % 1, 6
Differential Voltage Swing VSWING Averaging off 300 mV 2
Crossing Point Voltage VXABS Averaging off 300 446 550 mV 1,4,5
Crossing Point Variation VXABSVAR Averaging off 70 140 mV 1,4,9
Maximum Output Voltage VHIGH Averaging off 1150 mV 1,7
Minimum Output Voltage VLOW Averaging off -300 mV 1,8
Duty Cycle DCYC Averaging on 45 49.8 55 % 2
CPU Skew CPUSKEW Averaging on 35 100 ps
SRC Skew t
SKEWSRC
Averaging on, SRC to SATA skew when Byte0, bit 1 = 0 259 350 ps
1
Measurement taken for single ended waveform on a component test board (not in system)
2
Measurement taken from differential waveform on a component test board. (not in system)
3
Slew rate emastured through V_swing voltage range centered about differential zero
4
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
5
Only applies to the differential rising edge (Clock rising, Clock# falling)
7
The max voltage including overshoot.
8
The min voltage including undershoot.
9
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit
Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute
6
Matchin
applies to risin
ed
e rate for Clock and fallin
ed
e rate for Clock#. It is measured usin
a +/-75mV window centered on the avera
e cross point where Clock
rising meets Clock# falling. The median cross point is used to calculate the voltage
NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). C
L
= 2pF, Rs = 0 ohms.
Clock Jitter Specs - Low Power Differential Outputs, Commercial Temperature Range
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
CPU Jitter - Cycle to Cycle CPUJC2C Differential Measurement 50 85 ps 1
SRC/SATA Jitter - Cycle to Cycle SRCJC2C Differential Measurement 50 125 ps 1,2
DOT Jitter - Cycle to Cycle DOTJC2C Differential Measurement 50 250 ps 1
t
jphasePLL
PCIe Gen 1 35 86
ps (p-
p)
1,2,3
t
jphaseLo
PCIe Gen 2
10kHz < f < 1.5MHz
1.8 3
ps
(RMS)
1,2,3
t
jphaseHigh
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz)
2.3 3.1
ps
(RMS)
1,2,3
NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). C
L
= 2pF, Rs = 0 ohms.
1
JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system
performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured in a real system.
2
Phase jitter requirement: The designated Gen2 outputs will meet the reference clock jitter requirements from the PCI Express Gen2 Base Spec. The test is performed
on a component test board under quiet conditions with all outputs on.
SRC Phase Jitter
3
See http://www.pcisig.com for complete specs
