IDT
®
Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
16
Datasheet
Suggested Suggested termination resistors for various driving conditions are as
follows for transmission lines with Zo = 50 ohms:
Driving 1 load, Rs = 39 ohms
Driving 2 loads, Rs = 22 ohms
Driving 1 load, Rs = 39 ohms
Driving 2 loads, Rs = 22 ohms
27M SS and Non-SS outputs
REF Output
Test Load
Single Ended Outputs
CL=5pF
Rs
Zo
Rs
Zo
Rs
Zo
CL=5pF
CL=5pF
IDT
®
Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
17
Datasheet
Clock Periods Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
- c-c jitter -SSC -ppm error 0ppm +
pp
m error +SSC + c-c jitter
Absolute
Period
Short-term
Avera
g
e
Long-Term
Avera
g
e
Period
Long-Term
Avera
g
e
Short-term
Avera
g
e
Absolute
Period
Minimum Minimum Minimum Nominal Maximum Maximum Maximum
SRC 100
9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2
CPU 100
9.91400 9.99900 9.99900 10.00000 10.00100 10.05130 10.13630 ns 1,2
CPU 133
7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2
CPU 166
5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2
CPU 200
4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2
CPU 266
3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2
CPU 333
2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2
CPU 400
2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2
Clock Periods Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
- c-c jitter -SSC -ppm error 0ppm +
pp
m error +SSC + c-c jitter
Absolute
Period
Short-term
Avera
g
e
Long-Term
Avera
g
e
Period
Long-Term
Avera
g
e
Short-term
Avera
g
e
Absolute
Period
Minimum Minimum Minimum Nominal Maximum Maximum Maximum
SRC 100
9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2
CPU 100
9.91400 9.99900 10.00000 10.00100 10.13630 ns 1,2
CPU 133
7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2
CPU 166
5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2
CPU 200
4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2
CPU 266
3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2
CPU 333
2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2
CPU 400
2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2
DOT 96
10.16560 10.41560 10.41670 10.41770 10.66770 ns 1,2
Notes:
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All Lon
g
Term Accurac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that REFOUT is at 14.31818MHz
Signal Name Signal Name
Measurement Window
Units Notes
Symbol
Definition
Measurement Window
Units Notes
Symbol
Definition
IDT
®
Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
18
Datasheet
Test Clarification Table
Comments
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MODE
HW PIN
TEST
ENTRY BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
<2.0V X 0 0 NORMAL
>2.0V 0 X 0 HI-Z
>2.0V 0 X 1 REF/N
>2.0V 1 X 0 REF/N
>2.0V 1 X 1 REF/N
<2.0V X 1 0 HI-Z
<2.0V X 1 1 REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
HW S
W
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V then use TEST_SEL
If power-up w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control

9LRS3187BKILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK CALPELLA
Lifecycle:
New from this manufacturer.
Delivery:
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