IDT
®
Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
4
Datasheet
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
CPU
MHz
SRC
MHz
REF
MHz
DOT
MHz
0 (Default) 133.33
1 100.00
1. FS
L
C is a low-threshold input.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
100.00 14.318 96.00
Table 2: pin 6, 7 Configuration
Pin 6 Pin 7
Spread
MHz MHz %
000
27MHz_nonSS 27MHz_SS -1.75%
001
27MHz_nonSS 27MHz_SS
+-0.5%
010
27MHz_nonSS 27MHz_SS -0.5%
Default
011
27MHz_nonSS 27MHz_SS
-1%
100
27MHz_nonSS 27MHz_SS
-1.5%
101
27MHz_nonSS 27MHz_SS
-2%
110
27MHz_nonSS 27MHz_SS
-0.75%
111
27MHz_nonSS 27MHz_SS -1.25%
B1b3 B1b2 B1b1 Comment
Table 3: IO_Vout select table
B9b2 B9b1 B9b0 IO_Vout
000
0.3V
001
0.4V
010
0.5V
011
0.6V
100
0.7V
101
0.8V
110
0.9V
111
1.0V
IDT
®
Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
5
Datasheet
1
1
Enable Running Running Running Running
0
X Enable Low/20K Low Low/20K Low
1
0
Enable High Low High Low
1X
Disable
Low/20K Low Low/20K Low
Running Running Low/20K Low
CPU Power Management Table
PD# CPU_STOP#
SMBus
Re
g
. OE
CPU1 CPU1# CPU0 CPU0#
M1
SRC and DOT96MHz Power Management Table
0
X Enable Low/20K Low Low/20K Low
1 X Enable Running Running Running Running
1X
Disable
Low/20K Low Low/20K Low
Low/20K Low Low/20K Low
PD# CPU_STOP#
SMBus
Reg. OE
SRC SRC# DOT DOT#
M1
Singled-ended Power Management Table
1 X Enable Running Running
0
X Enable Low Hi-Z
1X
Disable
Low Low
Low Hi-Z
REFPD# CPU_STOP#
SMBus
Re
g
. OE
M1
27M
IDT
®
Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
6
Datasheet
General SMBus serial interface information for the ICS9LRS3187B
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
IDT clock will
acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will
acknowledge
Controller (host) sends the data byte count = X
IDT clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
IDT clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
IDT clock will
acknowledge
Controller (host) sends the begining byte
location = N
IDT clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
IDT clock will
acknowledge
IDT clock will send the data byte count = X
IDT clock sends
Byte N + X -1
IDT clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
IDT (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK

9LRS3187BKILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK CALPELLA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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