Si5100
Rev. 1.1 19
5.6. Auxiliary Clock Output
To support the widest range of system timing
configurations, The Si5601/Si5602 provides a primary
clock output (RXCLK1) and a secondary clock output
(RXCLK2). The RXCLK2 output can be configured to
provide a clock that is 1/16th or 1/64th the frequency of
the high-speed recovered clock. The divide ratio which
determines the RXCLK2 output frequency is selected by
RXCLK2DIV.
5.7. Receive Data Squelch
During some system error conditions, such as LOS, it
may be desirable to force the receive data output to
zero in order to avoid propagation of erroneous data
into the downstream electronics. The Si5100 provides a
data squelching control input, RXSQLCH
, for this
purpose.
When the RXSQLCH
input is low, the data outputs,
RXDOUT[15:0], are forced to a zero state. The
RXSQLCH
input is ignored when the device is operating
in diagnostic loopback mode (DLBK
=0).
6. Transmitter
The transmitter consists of a low-jitter clock multiplier
unit (CMU) with a serializer that operates in either a
16:1 or 4:1 configuration. The CMU uses a phase-
locked loop (PLL) architecture based on Silicon
Laboratories’ proprietary DSPLL technology. This
technology generates low jitter clock and data outputs
that provide significant margin to the SONET/SDH
specifications. The DSPLL architecture also utilizes a
digitally-implemented loop filter that eliminates the need
for external loop filter components. As a result, sensitive
noise coupling nodes that typically degrade jitter
performance in crowded PCB environments are
removed.
The DSPLL also reduces the complexity and relaxes
the performance requirements for reference clock
distribution circuitry for OC-48/STM-16 optical port
cards. The DSPLL provides selectable wideband and
narrowband loop filter settings that allow the jitter
attenuation characteristics of the CMU to be optimized
for the jitter content of the supplied reference clock. This
allows the CMU to operate with reference clocks that
have relatively high jitter content.
Unlike traditional analog PLL implementations, the loop
filter bandwidth of the Si5100 transmitter CMU is
controlled by a digital filter inside the DSPLL circuit
allowing the bandwidth to be changed without changing
any external component values.
6.1. DSPLL™ Clock Multiplier Unit
The Si5100’s clock multiplier unit (CMU) uses Silicon
Laboratories proprietary DSPLL technology to achieve
optimal jitter performance. The DSPLL implementation
utilizes a digital signal processing (DSP) algorithm to
replace the loop filter commonly found in analog PLL
designs. This algorithm processes the phase detector
error term and generates a digital control value to adjust
the frequency of the voltage-controlled oscillator (VCO).
The DSPLL implementation requires no external loop
filter components. Eliminating sensitive noise entry
points makes the DSPLL implementation less
susceptible to board-level noise sources and makes
SONET/SDH jitter compliance easier to attain in the
application.
The transmit CMU multiplies the frequency of the
selected reference clock up to the serial transmit data
rate. The TXLOL
output signal provides an indication of
the transmit CMU lock status. When the CMU has
achieved lock with the selected reference, the TXLOL
output is deasserted (driven high). The TXLOL signal is
asserted, indicating a transmit CMU loss-of-lock
condition when a valid clock signal is not detected on
the selected reference clock input. The TXLOL
signal is
also asserted during the transmit CMU frequency
calibration. Calibration is performed automatically when
the Si5100 is powered on, when a valid clock signal is
detected on the selected reference clock input following
a period when no valid clock was present, or when the
frequency of the selected reference clock is outside of
the transmit CMU’s PLL lock range, or after RESET is
deasserted.
6.1.1. Programmable Loop Filter Bandwidth
The digitally-implemented loop filter allows for four
transmit CMU loop bandwidth settings that provide
wideband or narrowband jitter transfer characteristics.
The filter bandwidth is selected via the BWSEL[1:0]
control inputs. The loop bandwidth choices are listed in
Table 6. Unlike traditional PLL implementations,
changing the loop filter bandwidth of the Si5100 is
accomplished without the need to change external
component values.
Lower loop bandwidth settings (Narrowband operation)
make the Si5100 more tolerant to jitter on the reference
clock source. As a result, circuitry used to generate and
distribute the physical layer reference clocks can be
simplified without compromising margin to the
SONET/SDH jitter specifications.
Higher loop bandwidth settings (Wideband operation)
are useful in applications where the reference clock is
provided by a low jitter source, such as the Si5364
Clock Synchronization IC or Si5320 Precision Clock
