MT16VDDF12864AY-40BJ1

PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64A.fm - Rev. B 11/07 EN
4 ©2007 Micron Technology, Inc. All rights reserved
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Table 6: Pin Descriptions
Symbol Type Description
A0–A12 Input Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command.
BA0, BA1 Input Bank address: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
Input Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates the internal clock, input buffers, and output drivers.
DM0–DM7 Input Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although DM pins are input-only,
the DM loading is designed to match that of DQ and DQS pins.
S0#, S1# Input Chip selects: S# (registered LOW) enables (registered HIGH) disables the
command decoder.
SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the
presence-detect device.
SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
DQ0–DQ63 I/O Data input/output: Data bus.
DQS0–DQS7 I/O Data strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, center-aligned with write data. Used to capture data.
SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
V
DD/VDDQ Supply Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
V
DDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
V
REF Supply SSTL_2 reference voltage (VDD/2).
VSS Supply Ground.
NC No connect: These pins are not connected on the module.
PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64A.fm - Rev. B 11/07 EN
5 ©2007 Micron Technology, Inc. All rights reserved
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
BA0, BA1
A0–A12
RAS#
CAS#
WE#
CKE1
CKE0
BA0, BA1: DDR SDRAM
A0–A12: DDR SDRAM
RAS#: DDR SDRAM
CAS#: DDR SDRAM
WE#: DDR SDRAM
CKE0: DDR SDRAM, rank 0
CKE1: DDR SDRAM, rank 1
VREF
VSS
DDR SDRAM
DDR SDRAM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U8
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U6
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U13
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U14
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U16
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
S0#
U3
U17
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
U15
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S1#
DM CS# DQS
DM CS# DQS DM CS# DQS
DM CS# DQS DM CS# DQS
DM CS# DQS
DQS0
DM4
DQS4
DM1
DQS1
DM5
DQS5
U12
DM CS# DQS
DM2
DQS2
DM6
DQS6
DM CS# DQS
DM CS# DQS
U11
U7
DM CS# DQS
DM CS# DQS
DM CS# DQS DM CS# DQS
DM3
DQS3
DM7
DQS7
U4
DM CS# DQS
U10
DM CS# DQS
VDD/VDDQ
DDR SDRAM
U4, U5,
U13, U14
CK0
CK0#
U1–U3,
U15–U17
CK1
CK1#
U6–U8,
U10–U12
CK2
CK2#
VDDSPD
SPD EEPROM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
A0
SPD EEPROM
A1 A2
SA0 SA1 SA2
SDA
SCL
WP
Vss
U19
Rank 0 = U1, U3, U6, U8, U11, U13, U14, U16
Rank 1 = U2, U4, U5, U7, U10, U12, U15, U17
PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64A.fm - Rev. B 11/07 EN
6 ©2007 Micron Technology, Inc. All rights reserved
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
General Description
General Description
The MT16VDDF6464A and MT16VDDF12864A are high-speed, CMOS, dynamic random
access 512MB and 1GB memory modules organized in a x64 configuration. These
modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
2
C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
SS on the
module, permanently disabling hardware write protect.

MT16VDDF12864AY-40BJ1

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR SDRAM 1GB 184UDIMM
Lifecycle:
New from this manufacturer.
Delivery:
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