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MT16VDDF12864AY-40BJ1

P1-P3P4-P6P7-P9P10-P11
PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64A.fm - Rev. B 11/07 EN
7 ©2007 Micron Technology, Inc. All rights reserved
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 7 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions outside those indicated on the device data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reliability.
Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to close timing budgets.
Component AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in Table 8.
Table 7: Absolute Maximum Ratings
Symbol Parameter Min Max Units
V
DD/VDDQVDD/VDDQ supply voltage relative to VSS –1.0 +3.6 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 +3.2 V
I
I Input leakage current; Any input 0V ≤ VIN ≤ VDD;
VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under
test = 0V)
Address inputs,
RAS#, CAS#, WE#, BA
–32 +32 µA
S#, CKE 16 16
CK0, CK0# –8 +8
CK1, CK1#, CK2, CK2# –12 +12
DM –4 +4
I
OZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are
disabled
DQ, DQS –10 +10 µA
T
A
DRAM ambient operating temperature
1
Commercial 0 +70 °C
Industrial –40 +85 °C
Table 8: Module and Component Speed Grades
Module Speed Grade Component Speed Grade
-40B -5B
-335 -6
-265 -75
PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64A.fm - Rev. B 11/07 EN
8 ©2007 Micron Technology, Inc. All rights reserved
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
IDD Specifications
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in I
DD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 9: IDD Specifications and Conditions – 512MB
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition Symbol -40B -335 -265 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0
1
1,112 1,032 992 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1
1
1,392 1,392 1,192 mA
Precharge power-down standby current: All device banks idle; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P
2
64 64 64 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock cycle;
V
IN
=V
REF
for DQ, DQS, and DM
IDD2F
2
960 800 720 mA
Active power-down standby current: One device bank active; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P
2
640 480 400 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle; Address and other control inputs changing once per clock
cycle
I
DD3N
2
1,120 960 800 mA
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); IOUT =0mA
IDD4R
1
1,632 1,432 1,232 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W
1
1,592 1,432 1,232 mA
Auto refresh current
t
REFC =
t
RFC (MIN) IDD5
2
4,160 4,080 3,760 mA
t
REFC = 7.8125µs IDD5A
2
96 96 96 mA
Self refresh current: CKE ≤ 0.2V IDD6
2
64 64 64 mA
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address
and control inputs change only during active READ or WRITE commands
IDD7
1
3,792 3,312 2,832 mA
PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64A.fm - Rev. B 11/07 EN
9 ©2007 Micron Technology, Inc. All rights reserved
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in I
DD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 10: IDD Specifications and Conditions – 1GB
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition Symbol -40B Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0
1
1,280 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1
1
1,520 mA
Precharge power-down standby current: All device banks idle; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P
2
80 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock
cycle; V
IN
=V
REF
for DQ, DQS, and DM
IDD2F
2
880 mA
Active power-down standby current: One device bank active; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P
2
720 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
I
DD3N
2
960 mA
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); IOUT =0mA
IDD4R
1
1,560 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W
1
1,600 mA
Auto refresh current
t
REFC =
t
RFC (MIN) IDD5
2
5,520 mA
t
REFC = 7.8125µs IDD5A
2
176 mA
Self refresh current: CKE ≤ 0.2V IDD6
2
80 mA
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
Address and control inputs change only during active READ or WRITE
commands
IDD7
1
3,640 mA
P1-P3P4-P6P7-P9P10-P11

MT16VDDF12864AY-40BJ1

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Manufacturer:
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Description:
MODULE DDR SDRAM 1GB 184UDIMM
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