BU1425AKV Datasheet BU1425AKV | P13-P15

Multimedia ICs BU1425AK / BU1425AKV

Table 5: Bit assignments in RGB Through mode

Output Pin

YOUT (45)

VOUT (39)

COUT (37)

BIT8

RD7

GD7

BD7

BIT7

RD6

GD6

BD6

BIT6

RD5

GD5

BD5

BIT5

RD4

GD4

BD4

BIT4

RD3

GD3

BD3

BIT3

RD2

GD2

BD2

BIT2

RD1

GD1

BD1

BIT1

RD0

GD0

BD0

BIT0

ROSD

GOSD

BOSD

The BU1425AK / AKV has an internal OSD switch and

chrominance data generating function. Consequently,

joint usage of an OSD-IC with blanking and R, G, and B

output can be easily supported by the OSD. Moreover,

a clock with half the internal processing frequency of

the BU1425AK is output from the PIXCLK pin, and can

be connected to the OSD-IC clock input, enabling the

timing to be captured.

ROSD, GOSD, and BOSD pin input is effective as long

as the OSDSW pin input is HIGH. The relationship

between OSD data and chrominance data is as shown

in Table 6 below.

Table 6: Correspondence between OSD function, input data and chrominance output

OSDSW ROSD

∗

GOSD

∗

BOSD

∗

Output Chrominance Signal

Black (blanking)

Blue

Green

Cyan

Red

Magenta

Yellow

White

Based on input specified by IM0 and IM1

4) Clock modes

With the BU1425AK / AKV, clock input is available at the

VCLK pin.

Clocks supplied from an external source should basically

be input at a frequency double that of clocks used inter-

nally (basic clock: BCLK) (when the CLKSW pin is LOW).

The phase relationship between the internal clock and

the external clock at this time is as shown in Fig. 3, with

the HSY pin input serving as a reference. In the Master

mode, in which data from the HSY pin is output and

used, HSY is output at the timing shown in Fig. 3. With

the BU1425AK, data (RD, GD, BD, etc.) is read at the ris-

ing edge of the internal clock (BCLK), so data should be

input to the BU1425AK / AKV as shown in Fig. 3.

HSY

VCLK

Internal clock (BCLK)

Input data

Fig. 3 Illustration of clock timing (CLKSW is LOW)

Multimedia ICs BU1425AK / BU1425AKV

Also, setting the CLKSW pin to HIGH enables the fre-

quency of the external clock to be used as BCLK, the

internal clock, just as it is. Since the data is read to the

BU1425AK / AKV at the rising edge of BCLK at this

time as well, data should be input as shown in Fig. 4.

The relationship with HSY is also as shown in Fig. 4.

HSY

VCLK

Internal clock (BCLK)

Input data

Fig. 4 Illustration of clock timing (CLKSW is HIGH)

With the BU1425AK / AKV, the sub-carrier (burst) fre-

quency is generated using the internal clock. For this

reason, the frequencies used in the various modes are

limited, so those frequencies should be input (see Table

7 below).

Table 7: BU1425AK / AKV clock input frequency settings

CLKSW Pin

Video-CD Mode

27.000MHz

13.500MHz

CD-G Mode

Same for NTSC / PAL / PAL60 NTSC

28.636MHz

14.318MHz

PAL / PAL60

28.3750MHz

14.1875MHz

5) Synchronization signals

The BU1425AK / AKV has an "Encoder Master" mode in

which synchronization signals are output, and an

"Encoder Slave" mode in which synchronization signals

are input from an external source and used to achieve

synchronization. These modes are switched at the

SLABEB pin. When the SLABEB pin is LOW, the Slave

mode is in effect, and when HIGH, the Master mode is in

effect.

In the Master mode, the HSY and VSY pins serve as out-

put, with horizontal synchronization signals (HSYNC)

being output from the HSY pin and vertical synchroniza-

tion signals (VSYNC) from the VSY pin. At this time, the

reference timing for synchronization signal output is

determined at the rising edge of the RSTB pin. Output is

obtained in accordance with the specified mode (NTSC,

PAL, or PAL60, interlace or non-interlace). Output in the

non-interlace mode, however, is output only under "Odd"

field conditions (the falling edges of Hsy and Vsy are the

same).

In the Slave mode, the HSY and VSY pins serve as input,

and horizontal synchronization signals (HSYNC) should

be input to the HSY pin and vertical synchronization sig-

nals (VSYNC) to the VSY pin. The input synchronization

signals at this time should be input in accordance with

the specified mode. With the BU1425AK / AKV, field dis-

tinction between odd and even fields is made automati-

cally for each field when interlace input is used. With the

BU1425AK, all synchronization signals are treated as

negative polarity signals (signals for which the sync inter-

val goes LOW). When using the non-interlace mode,

operation is normally carried out under odd field condi-

tions (the falling edges of Hsy and Vsy are simultane-

ous).

Multimedia ICs BU1425AK / BU1425AKV

6) Y filter

With the BU1425AK / AKV, the frequency characteristic

of Y, which is mixed with the VOUT pin output, is set so

that it can be selected using the YFILON1B and 2B pins.

A through filter is normally used on the YOUT pin output,

so that it is not limited to this method.

Table 8: Frequency characteristic of the Y channel

YFILON2B YFILON1B

TRAP filter through

(same signal as YOUT pin output is mixed with VOUT)

Frequency characteristic of the Y channel

chart1

chart2

chart3

100

–40

20000100001000

AMPLITUDE (dB)

PHASE (deg)

FREQUENCY (kHz)

–5

–10

–15

– 20

– 25

– 30

– 35

180

135

– 45

–90

– 135

– 180

Gain-Phase Graphic

Fig.5 chart1 (BCLK = 13.5MHz)

100

–40

20000100001000

AMPLITUDE (dB)

FREQUENCY (kHz)

–5

–10

–15

–20

–25

–30

–35

PHASE (deg)

180

135

–45

– 90

– 135

– 180

Gain-Phase Graphic

Fig.6 chart2 (BCLK = 13.5MHz)

100

–40

20000100001000

AMPLITUDE (dB)

FREQUENCY (kHz)

–5

–10

–15

–20

–25

–30

–35

PHASE (deg)

180

135

–45

–90

– 135

– 180

Gain-Phase Graphic

Fig.7 chart3 (BCLK = 14.318MHz)

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BU1425AKV

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