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Multimedia ICs BU1425AK / BU1425AKV
4) Odd / even recognition timing in Slave mode
1. Timing based on recognition of odd conditions
The BU1425AK / AKV distinguishes whether the condi-
tions of each field (each time that VSY is input) are odd
or otherwise, and internal operation is carried out based
on that recognition after the data is input. As a result,
HSY and VSY are input under input conditions appropri-
ate to the specified mode, enabling regulated output for
the first time. Odd input conditions are indicated below.
Timing that does not match these conditions is recog-
nized as an even field.
VSY Delay from HSY
Parameter Symbol Max.Typ.Min.
Tvl ——128VSY input L interval
Thvdiff
Unit
BCLK
BCLK
HSY Rising edge
– 2clk
—
HSY falling edge
– 1clk
∗
BCLK = One cycle of internal clock
