Pin No. Pin name Equivalent circuitI / O Function
27 VSY I / O
Vertical synchronization signals (Vsync)
are input (when SLABEB = LOW) or
output (when SLABEB = HIGH) here.
35 VREF-C I
This is the reference voltage generator
circuit monitoring pin which deter-
mines the output amplitude (output cur-
rent for 1 LSB) of the DAC. A 0.01µF
capacitor should be attached between
this and pin 43 (AV
DD).
29 PIXCLK O
The internal processing clock is divid-
ed in half and output. Data is read at
the point at which the edge of this
clock changes. This can also be used
as the clock for the OSD IC.
32 INT I
This pin switches between interlace
(when HIGH) and non-interlace (when
LOW) modes. This pin is effective in
both the VIDEO-CD and CD-G
modes.
33
34
SLABEB
ADDH
I
I
This pin switches between the Master
(when HIGH) and Slave (when LOW)
modes. It is effective in the non-
interlace mode, and it switches bet-
ween – 0.5 lines (when LOW) and + 0.5
lines (when HIGH) for the number of
lines in an interlace field.
28 HSY I / O
This is the horizontal synchronization
signal pin. Negative polarity Hsync
signals are input (when SLABEB =
LOW) or output (when SLABEB =
HIGH) here. This is also used as the
synchronization signal for fixing the
PIXCLK output phase.
37 COUT O
This is the chrominance output pin for
the S pin.
