ADP3162JR-REEL Datasheet ADP3162JR-REEL, ADP3162JRZ-REEL7 | P1-P3

REV. A

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reliable. However, no responsibility is assumed by Analog Devices for its

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may result from its use. No license is granted by implication or otherwise

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ADP3162

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2001

5-Bit Programmable 2-Phase

Synchronous Buck Controller

FUNCTIONAL BLOCK DIAGRAM

2-PHASE

DRIVER

LOGIC

UVLO

& BIAS

3.0V

REFERENCE

OSCILLATOR

SET

RESET

CROWBAR

VCC

REF

GND

COMP

PWM1

PWM2

PWRGD

CS–

CS+

VID

DAC

VID3 VID2 VID1 VID0 VID25

CMP

DAC–18%

DAC+24%

ADP3162

CMP1

CMP2

CMP3

FEATURES

ADOPT™ Optimal Positioning Technology for Superior

Load Transient Response and Fewest Output

Capacitors

Complies with VRM 8.5 with Lowest System Cost

Active Current Balancing Between Both Output Phases

5-Bit Digitally Programmable 1.05 V to 1.825 V Output

Dual Logic-Level PWM Outputs for Interface to

External High-Power Drivers

Total Output Accuracy ⴞ0.8% Over Temperature

Current-Mode Operation

Short Circuit Protection

Power Good Output

Overvoltage Protection Crowbar Protects

Microprocessors with No Additional

External Components

APPLICATIONS

Desktop PC Power Supplies for:

Intel Tualatin Processors

VRM Modules

GENERAL DESCRIPTION

The ADP3162 is a highly efficient dual output synchronous

buck switching regulator controller optimized for converting a

5 V or 12 V main supply into the core supply voltage required by

high-performance processors such as Tualatin. The ADP3162

uses an internal 5-bit DAC to read a voltage identification (VID)

code directly from the processor, which is used to set the output

voltage between 1.05 V and 1.825 V. The ADP3162 uses a

current mode PWM architecture to drive two logic-level outputs

at a programmable switching frequency that can be optimized

for VRM size and efficiency. The output signals are 180 degrees

out of phase, allowing for the construction of two complementary

buck switching stages. These two stages share the dc output

current to reduce overall output voltage ripple. An active cur-

rent balancing function ensures that both phases carry equal

portions of the total load current, even under large transient

loads, to minimize the size of the inductors.

The ADP3162 also uses a unique supplemental regulation tech-

nique called active voltage positioning to enhance load transient

performance. Active voltage positioning results in a dc/dc converter

that meets the stringent output voltage specifications for high

performance processors, with the minimum number of output

capacitors and smallest footprint. Unlike voltage-mode and

standard current-mode architectures, active voltage positioning

adjusts the output voltage as a function of the load current so

that it is always optimally positioned for a system transient. The

ADP3162 also provides accurate and reliable short circuit pro-

tection and adjustable current limiting.

The ADP3162 is specified over the commercial temperature

range of 0°C to 70°C and is available in a 16-lead narrow body

SOIC package.

ADOPT is a trademark of Analog Devices, Inc.

REV. A

–2–

ADP3162–SPECIFICATIONS

= 12 V, I

REF

= 150 ␮A, T

= 0ⴗC to 70ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

FEEDBACK INPUT

Accuracy V

1.05 V Output Figure 1 1.042 1.050 1.058 V

1.5 V Output Figure 1 1.488 1.500 1.512 V

1.825 V Output Figure 1 1.811 1.825 1.839 V

Line Regulation ∆V

VCC = 10 V to 14 V 0.05 %

Input Bias Current I

550 nA

Crowbar Trip Threshold V

CROWBAR

Percent of Nominal DAC Voltage 114 124 134 %

Crowbar Reset Threshold Percent of Nominal DAC Voltage 50 60 70 %

Crowbar Response Time t

CROWBAR

Overvoltage to PWM Going Low 300 ns

FB Low Foldback Threshold V

FB(LOW)

425 500 575 mV

REFERENCE

Output Voltage V

REF

0 ≤ I

REF

≤ 300 µA 2.952 3.0 3.048 V

Output Current I

REF

300 µA

VID INPUTS

Input Low Voltage V

IL(VID)

0.6 V

Input High Voltage V

IH(VID)

2.2 V

Input Current I

VID

VID(x) = 0 V 280 400 µA

Pull-Up Resistance R

VID

12 17 kΩ

Internal Pull-Up Voltage 2.7 3 3.3 V

OSCILLATOR

Maximum Frequency

CT(MAX)

2000 kHz

Frequency Accuracy f

= 25°C, CT = 91 pF 430 500 570 kHz

CT Charge Current I

= 25°C, V

in Regulation 130 150 170 µA

= 25°C, V

= 0 V 26 36 46 µA

ERROR AMPLIFIER

Output Resistance R

O(ERR)

200 kΩ

Transconductance g

m(ERR)

2.0 2.2 2.45 mmho

Output Current I

O(ERR)

FB = 0 V 1 mA

Maximum Output Voltage V

COMP(MAX)

FB Forced to V

OUT

– 3% 3.0 V

Output Disable Threshold V

COMP(OFF)

640 800 880 mV

–3 dB Bandwidth BW

ERR

COMP = Open 500 kHz

CURRENT SENSE

Threshold Voltage V

CS(TH)

CS+ = VCC, 69 79 89 mV

FB Forced to V

OUT

– 3%

0.8 V ≤ COMP ≤ 1 V 0 15 mV

CS(FOLD)

FB ≤ 375 mV 37 47 58 mV

∆V

COMP

/∆V

1 V ≤ V

COMP

≤ 3 V 25 V/V

Input Bias Current I

CS+

, I

CS–

CS+ = CS– = VCC 0.5 5 µA

Response Time t

CS+ – (CS–) ≥ 89 mV 50 ns

to PWM Going Low

POWER GOOD COMPARATOR

Undervoltage Threshold V

PWRGD(UV)

Percent of Nominal Output 76 82 88 %

Overvoltage Threshold V

PWRGD(OV)

Percent of Nominal Output 114 124 134 %

Output Voltage Low V

OL(PWRGD)

PWRGD(SINK)

= 100 µA 30 200 mV

Response Time 200 ns

PWM OUTPUTS

Output Voltage Low V

OL(PWM)

PWM(SINK)

= 400 µA 100 500 mV

Output Voltage High V

OH(PWM)

PWM(SOURCE)

= 400 µA 4.5 5.0 5.5 V

Output Current I

PWM

0.4 1 mA

Duty Cycle Limit

DC Per Phase, Relative to f

50 %

REV. A

–3–

ADP3162

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY

DC Supply Current

Normal Mode I

3.8 5.5 mA

UVLO Mode I

CC(UVLO)

VCC ≤ V

UVLO

, VCC Rising 220 400 µA

UVLO Threshold Voltage V

UVLO

5.9 6.4 6.9 V

UVLO Hysteresis 0.1 0.4 0.6 V

NOTES

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

Guaranteed by design, not tested in production.

Speciﬁcations subject to change without notice.

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1–4, VID3 –VID0, Voltage Identiﬁcation DAC Inputs.

5 VID25 These pins are pulled up to an internal

reference, providing a Logic 1 if left open.

The DAC output programs the FB regula-

tion voltage from 1.05 V to 1.825 V.

6 COMP Error Ampliﬁer Output and Compensation

Point. The voltage at this output programs

the output current control level between

CS+ and CS–.

7 FB Feedback Input. Error ampliﬁer input for

remote sensing of the output voltage.

8 CT External capacitor CT connection to ground

sets the frequency of the device.

9 GND Ground. All internal signals of the ADP3162

are referenced to this ground.

10 PWRGD Open drain output that signals when the out-

put voltage is in the proper operating range.

11 CS+ Current Sense Positive Node. Positive input

for the current comparator. The output

current is sensed as a voltage at this pin with

respect to CS–.

12 PWM2 Logic-level output for the Phase 2 driver.

13 PWM1 Logic-level output for the Phase 1 driver.

14 CS– Current Sense Negative Node. Negative

input for the current comparator.

15 REF 3.0 V Reference Output.

16 VCC Supply Voltage for the ADP3162.

ABSOLUTE MAXIMUM RATINGS*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

All Other Inputs and Outputs . . . . . . . . . . . . . –0.3 V to +10 V

Operating Ambient Temperature Range . . . . . . . 0°C to 70°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W

Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged. Unless otherwise speciﬁed, all voltages are referenced

to GND.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

ADP3162

VCC

REF

GND

COMP

PWM1

PWM2

PWRGD

CS–

CS+

VID3

VID2

VID1

VID0

VID25

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADP3162JR 0°C to 70°C Narrow Body SOIC R-16A (SO-16)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADP3162 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

P1-P3 P4-P6 P7-P9 P10-P12

ADP3162JR-REEL

Mfr. #:

Buy ADP3162JR-REEL

Manufacturer:

ON Semiconductor

Description:

IC REG CTRLR INTEL 2OUT 16SOIC

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ADP3162JR-REEL

ADP3162JR-REEL

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