ADP3162JR-REEL Datasheet ADP3162JR-REEL, ADP3162JRZ-REEL7 | P4-P6

REV. A

ADP3162

–4–

–Typical Performance Characteristics

CT CAPACITOR –

10000

1000

100

OSCILLATOR FREQUENCY – kHz

100

200 300 400 500

TPC 1. Oscillator Frequency vs. Timing Capacitor

OSCILLATOR FREQUENCY – kHz

4.10

3.90

3.85

0 2000

SUPPLY CURRENT – mA

1000

3.95

4.00

4.05

250 500 750 1250 1500 1750

TPC 2. Supply Current vs. Oscillator Frequency

OUTPUT ACCURACY – % OF NOMINAL

–0.5 0.5

NUMBER OF PARTS – %

= 25⬚C

OUT

= 1.6V

TPC 3. Output Accuracy Distribution

REV. A

ADP3162

–5–

VCC

REF

GND

COMP

PWM1

PWM2

PWRGD

CS–

CS+

VID3

VID2

VID1

VID0

VID25

ADP3162

5-BIT CODE

1 F

4.7nF

1.2V

12V

100nF

AD820

Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit

Table I. Output Voltage vs. VID Code

VID25 VID3 VID2 VID1 VID0 V

OUT(NOM)

00100 1.050 V

10100 1.075 V

00011 1.100 V

10011 1.125 V

00010 1.150 V

10010 1.175 V

00001 1.200 V

10001 1.225 V

00000 1.250 V

10000 1.275 V

01111 1.300 V

11111 1.325 V

01110 1.350 V

11110 1.375 V

01101 1.400 V

11101 1.425 V

01100 1.450 V

11100 1.475 V

01011 1.500 V

11011 1.525 V

01010 1.550 V

11010 1.575 V

01001 1.600 V

11001 1.625 V

01000 1.650 V

11000 1.675 V

00111 1.700 V

10111 1.725 V

00110 1.750 V

10110 1.775 V

00101 1.800 V

10101 1.825 V

THEORY OF OPERATION

The ADP3162 combines a current-mode, fixed frequency PWM

controller with antiphase logic outputs in a controller for a two-

phase synchronous buck power converter. Two-phase operation

is important for switching the high currents required by high

performance microprocessors. Handling the high current in a

single-phase converter would place difficult requirements on the

power components such as inductor wire size, MOSFET ON-

resistance and thermal dissipation. The ADP3162’s high side

current sensing topology ensures that the load currents are bal-

anced in each phase, such that neither phase has to carry more

than half of the power. An additional benefit of high side current

sensing over output current sensing is that the average current

through the sense resistor is reduced by the duty cycle of the

converter allowing the use of a lower power, lower cost resistor.

The outputs of the ADP3162 are logic drivers only and are

not intended to directly drive external power MOSFETs.

Instead, the ADP3162 should be paired with drivers such as

the ADP3412, ADP3413, or ADP3414.

The frequency of the ADP3162 is set by an external capacitor

connected to the CT pin. Each output phase of the ADP3162

operates at half of the frequency set by the CT pin. The error

amplifier and current sense comparator control the duty cycle of

the PWM outputs to maintain regulation. The maximum duty

cycle per phase is inherently limited to 50% because the PWM

outputs toggle in two-phase operation. While one phase is on,

the other phase is off. In no case can both outputs be high at the

same time.

Output Voltage Sensing

The output voltage is sensed at the FB pin allowing for remote

sensing. To maintain the accuracy of the remote sensing, the

GND pin should also be connected close to the load. A voltage

error ampliﬁer (g

) ampliﬁes the difference between the output

voltage and a programmable reference voltage. The reference

voltage is programmed between 1.05 V and 1.825 V by an internal

5-bit DAC, which reads the code at the voltage identiﬁcation

(VID) pins. (Refer to Table I for the output voltage versus VID pin

code information.)

Active Voltage Positioning

The ADP3162 uses Analog Devices Optimal Positioning Tech-

nology (ADOPT), a unique supplemental regulation technique

that uses active voltage positioning and provides optimal com-

pensation for load transients. When implemented, ADOPT adjusts

the output voltage as a function of the load current, so that it is

always optimally positioned for a load transient. Standard (passive)

voltage positioning has poor dynamic performance, rendering

it ineffective under the stringent repetitive transient conditions

required by high performance processors. ADOPT, however,

provides optimal bandwidth for transient response that yields

optimal load transient response with the minimum number of

output capacitors.

Reference Output

A 3.0 V reference is available on the ADP3162. This reference

is normally used to set the voltage positioning accurately using a

resistor divider to the COMP pin. In addition, the reference can

be used for other functions such as generating a regulated voltage

with an external ampliﬁer. The reference is bypassed with a 1 nF

capacitor to ground. It is not intended to supply current to large

capacitive loads, and it should not be used to provide more than

1 mA of output current.

REV. A

ADP3162

–6–

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),

the voltage-error ampliﬁer and the current comparator are the

main control elements. The voltage at the CT pin of the oscilla-

tor ramps between 0 V and 3 V. When that voltage reaches 3 V,

the oscillator sets the driver logic, which sets PWM1 high. Dur-

ing the ON time of Phase 1, the driver IC turns on the high-side

MOSFET. The CS+ and CS– pins monitor the current through

the sense resistor that feeds both high-side MOSFETs. When

the voltage between the two pins exceeds the threshold level

set by the voltage error amplifier (g

), the driver logic is reset

and the PWM output goes low. This signals the driver IC to turn

off the high-side MOSFET and turn on the low-side MOSFET.

On the next cycle of the oscillator, the driver logic toggles and

sets PWM2 high. On each following cycle of the oscillator, the

outputs toggle between PWM1 and PWM2. In each case, the

current comparator resets the PWM output low when the current

comparator threshold is reached. As the load current increases,

the output voltage starts to decrease. This causes an increase in

the output of the g

ampliﬁer, which in turn leads to an increase

in the current comparator threshold, thus programming more

current to be delivered to the output so that voltage regulation is

maintained.

Active Current Sharing

The ADP3162 ensures current balance in the two phases by

actively sensing the current through a single sense resistor. During

one phase’s ON time, the current through the respective high-side

MOSFET and inductor is measured through the sense resistor

(R4 in Figure 2). When the comparator (CMP1 in the Functional

Block Diagram) threshold programmed by the g

amplifier is

reached, the high-side MOSFET turns off. In the next cycle the

ADP3162 switches to the second phase. The current is measured

with the same sense resistor and the same internal comparator,

ensuring accurate matching. This scheme is immune to imbalances

in the MOSFETs’ R

DS(ON)

and inductors’ parasitic resistances.

If for some reason one of the phases fails, the other phase will still

be limited to its maximum output current (one-half of the short

circuit current limit). If this is not sufﬁcient to supply the load,

the output voltage will droop and cause the PWRGD output to

signal that the output voltage has fallen out of its speciﬁed range.

Short Circuit Protection

The ADP3162 has multiple levels of short circuit protection to

ensure fail-safe operation. The sense resistor and the maximum

current sense threshold voltage given in the speciﬁcations set the

peak current limit.

When the load current exceeds the current limit, the excess current

discharges the output capacitor. When the output voltage is below

the foldback threshold V

FB(LOW)

, the maximum deliverable output

current is cut by reducing the current sense threshold from the

current limit threshold, V

CS(CL)

, to the foldback threshold,

CS(FOLD)

. Along with the resulting current foldback, the oscilla-

tor frequency is reduced by a factor of five when the output is

0 V. This further reduces the average current in short circuit.

Power-Good Monitoring

The Power-Good comparator monitors the output voltage of the

supply via the FB pin. The PWRGD pin is an open drain output

whose high level (when connected to a pull-up resistor) indi-

cates that the output voltage is within the specified range of

the nominal output voltage requested by the VID DAC. PWRGD

will go low if the output is outside this range.

Output Crowbar

The ADP3162 includes a crowbar comparator that senses when

the output voltage rises higher than the specified trip thresh-

old, V

CROWBAR

. This comparator overrides the control loop and

sets both PWM outputs low. The driver ICs turn off the high side

MOSFETs and turn on the low-side MOSFETs, thus pulling the

output down as the reversed current builds up in the inductors. If

the output overvoltage is due to a short of the high side MOSFET,

this action will current limit the input supply or blow its fuse,

BST

DLY

VCC

DRVH

PGND

DRVL

ADP3412

ADP3162

19.1k⍀

10.1k⍀

3.3nF

CC(CORE)

1.7V

30A

CC(CORE)

RTN

C19

C18C17 C29

1000␮F ⴛ 8

RUBYCON ZA SERIES

24m⍀ ESR (EACH)

C16

C20 C27 C28

MBR052LTI

FMMT18

1␮H

IRL3803

C10

1␮F

MBR052LTI

15pF

1␮F

ZMM5236BCT

2.4k⍀

330⍀

C23

330pF

C22 1nF

4.7␮F

10⍀

C21

15nF

C13C12

RTN

C26

4.7␮F

15pF

1␮F

20⍀

4m⍀

100pF

91pF

1k⍀

VID3

VID2

VID1

VID0

VID25

COMP

VCC

REF

CS–

PWM1

PWM2

CS+

PWRGD

GND

BST

DLY

VCC

DRVH

PGND

DRVL

ADP3412

FROM

CPU

IRL3803

12V V

+ +

C14 C15

IRL3803

1000␮F ⴛ 4

Figure 2. 23 A Pentium

III CPU Supply Circuit

Pentium is a registered trademark of Intel Corporation.

P1-P3 P4-P6 P7-P9 P10-P12

ADP3162JR-REEL

Mfr. #:

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Manufacturer:

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IC REG CTRLR INTEL 2OUT 16SOIC

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ADP3162JR-REEL

ADP3162JR-REEL

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