1
®
FN6413.1
ISL8723, ISL8724
Power Sequencing Controllers
The Intersil ISL8723 and ISL8724 are 4 channel sequencers
controlling the on and off sequence of voltages with
undervoltage supply fault protection and a “sequence
completed” signal (RESET
). For larger systems, more than 4
voltages can be sequenced by a simple connection of
multiple IC's. These sequencers use an integrated charge
pump to drive 4 external low-cost N-channel MOSFET
switch gates above the IC bias voltage by 5.3V. These IC's
can be biased from and control any supply from 2.5V to 5V
and additionally monitor any voltage above 0.7V. Individual
product descriptions follow.
The four channel ISL8723 (ENABLE input), ISL8724
(ENABLE
input) offer the designer 4 voltage control when it
is required that all four rails are in minimal compliance prior
to turn on and that compliance must be maintained during
operation. The ISL8723 has a low power standby mode
when it is disabled suitable for battery powered applications.
External resistors provide flexible voltage threshold
programming of monitored voltages. Delay and sequencing
timing are programmable by external capacitors for both
ramp up and ramp down.
Features
Enables arbitrary turn-on and turn-off sequencing of up to
four power supplies (0.7V to 5V)
Operates from 2.5V to 5V supply voltage
Supplies V
DD
+5.3V of charge pumped gate drive
Adjustable voltage slew rate for each rail
Multiple sequencers can be easily daisy-chained to
sequence an infinite number of independent voltages
Glitch immunity
Undervoltage lockout for each monitored supply voltage
30µA Sleep State (ISL8723)
Active high (ISL8723) or low (ISL8724) ENABLE
input
Pb-free (RoHS compliant)
Applications
Graphics cards
FPGA/ASIC/microprocessor/PowerPC supply sequencing
Network Routers
Telecommunications Systems
Pinout
ISL8723, ISL8724
(24 LD QFN)
TOP VIEW
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL8723IRZ* 87 23IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4
ISL8724IRZ* 87 24IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4
ISL8723EVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
1
2
3
4
5
6
18
17
16
15
14
13
24 23 22 21 20 19
7 8 9 10 11 12
4mmx4mm
ENABLE/
ENABLE
GATE_A
DLY_OFF_C
DLY_OFF_D
GATE_B
GATE_C
GATE_D
DLY_ON_B
NC
GND
NC
UVLO_B
DLY_OFF_B
UVLO_D
DLY_ON_D
DLY_ON_C
UVLO_C
DLY_OFF_A
GND
UVLO_A
DLY_ON_A
SYSRST
VDD
RESET
Data Sheet April 22, 2009
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2009. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
2
FN6413.1
April 22, 2009
FIGURE 1. TYPICAL ISL8723 APPLICATION
USAGE
FIGURE 2. ISL8723 BLOCK DIAGRAM (1/4)
Pin Descriptions
PIN
#
PIN
NAME FUNCTION DESCRIPTION
23 VDD Chip Bias Bias IC from nominal 2.5V to 5V
10, 19 GND Bias Return IC ground.
NOTE: Pin 19 internally tied to GND with 6kΩ. This pin can be tied to GND or left open.
1 ENABLE/
ENABLE
Input to start on/off
sequencing
Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is
disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE
.
24 RESET
RESET Output RESET provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization
of output voltages. RESET
will assert low upon any UVLO not being satisfied or ENABLE/ENABLE being
deasserted. The RESET
output is an open drain N-channel FET and is guaranteed to be in the correct
state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X.
20 UVLO_A Undervoltage Lock
Out/Monitoring
Input
These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and
are filtered to ignore short (<7µs) transients below programmed UVLO level.
12 UVLO_B
17 UVLO_C
14 UVLO_D
21 DLY_ON_A Gate On Delay
Timer Output
Allows for programming the delay and sequence for V
OUT
turn-on using a capacitor to ground. Each
cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE
with an internal current
source providing delayed enhancement of the associated FETs GATE to turn-on.
8DLY_ON_B
16 DLY_ON_C
15 DLY_ON_D
AOUTAIN
BIN
CIN
DIN
BOUT
COUT
DOUT
UVLO_B
UVLO_A
UVLO_D
UVLO_C
AIN
DLY_ON_A
DLY_OFF_A
DLY_OFF_B
DLY_OFF_C
DLY_OFF_D
DLY_ON_B
DLY_ON_C
DLY_ON_D
ENABLE
SYSRST
GROUND
BIN
CIN
DIN
RESET
V
DD
GATE D
GATE C
GATE B
GATE A
EN
SYSRST
UVLOX
0.633V
RESET
DLY_ONX
1.26V
DLY_OFFX
1.26V
GATEX
LOGIC
10µA
BIAS
LOCK OUT
VDD
RISING DELAY
VDD+5V
Q-PUMP
1µA
1µA
-10µA
30µs
FILTER
150ms
RISING DELAY
10ms
ISL8723, ISL8724
3
FN6413.1
April 22, 2009
18 DLY_OFF_A Gate Off Delay
Timer Output
Allows for programming the delay and sequence for V
OUT
turn-off through ENABLE/ENABLE via a
capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down thus turning-off the FET.
13 DLY_OFF_B
3 DLY_OFF_C
4 DLY_OFF_D
2 GATE_A FET Gate Drive
Output
Drives the external FETs with a 10µA current source to soft start ramp into the load. During sequence
off, 10µA is sunk from this pin to control the FET turn-off. During a turn-off due to a fault, the gate will
sink ~75mA to ensure a rapid turn-off.
5GATE_B
6GATE_C
7GATE_D
22 SYSRST
System Reset I/O As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This pin
can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from
input signal on this pin being driven high to first GATE.
As an output when there is a UV condition this pin pulls low. If common to other SYSRST
pins in a multiple
IC configuration it will cause immediate and unconditional latch-off of all other GATEs on all other ISL872x
sequencers.
This pin is released to go high once all UVLO and enable conditions are satisfied and is pulled low
concurrent with the last GATE being turned off after EN disabled.
9, 11 No Connect No Connect No Connect
Pin Descriptions (Continued)
PIN
#
PIN
NAME FUNCTION DESCRIPTION
ISL8723, ISL8724

ISL8723EVAL1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Power Management IC Development Tools ISL8723 EVAL BRD 1
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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