8
FN6413.1
April 22, 2009
Using the ISL8723EVAL1 Platform
The ISL8723EVAL1 platform allows evaluation of the
ISL8723, easily providing access to the critical nodes (see
Figure 22 for schematic and Figure 23 for a photograph of
the evaluation platform).
The board has a SMD layout with a ISL8723 illustrating the
possible small implementation size for a typical four rail
sequencing application. There are bias and function labeled
test points to give access to the IC pins for evaluation.
Remember that significant current or capacitive loading of
particular I/O pins will affect functionality and performance.
The default configuration of the ISL8723EVAL1 circuit was
built around the following design assumptions:
1. Using the ISL8723IR
2. The four supplies being sequenced are 5V (IN_A), 3.3V
(IN_B), 2.5V (IN_D) and 1.5V (IN_C), the UVLO levels
are ~80% of nominal voltages. Resistors chosen such
that the total resistance of each divider is ~ 10k using
standard value resistors to approximate 80% of
nominal voltage supply = 0.63V on UVLO input.
3. The desired order turn-on sequence is 5V first, then 3.3V
about 12ms later then the 2.5V supply about 19ms later
and lastly the 1.5V supply about 40ms later.
4. The desired turn-off sequence is first the 2.5V, the 3.3V
12ms later, then the 1.5V supply about 36ms later and
lastly the 5V supply about 72ms after that.
5. LED off indicates sequence has completed and RESET
has released and pulled high.
All scope shots are taken from ISL8723EVAL1 board.
Figures 13 and 14 illustrate the desired turn-on and turn-off
sequences respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values so other than that illustrated can be accomplished.
Figures 15 and 16 illustrate the timing relationships between
the EN input, RESET
, DLY and GATE outputs and the VOUT
voltage for a single channel being turned on and off
respectively.
RESET
and SYSRST functionality and relationships are
shown in Figures 17 through 21.
Figure 17 illustrates that with a rising VDD, EN tied to VDD,
and all UVLO configured to be satisfied, both the RESET
and
SYSRST
are held low before V
DD
= 1V. SYSRST is released
to go high once the last UVLO is satisfied and RESET
is
released to go high at t
RSTdel
after the last GATE is high.
Figure 18 shows GATE and RESET
response to SYSRST
being pulled low.
Figure 19 shows EN high to SYSRST delay with all UVLO
inputs satisfied.
Figure 20 shows RESET
and SYSRST delay to EN pulled low.
Figure 21 shows ~8µs of glitch filter duration, t
FIL
during
which the RESET
and SYSRST do not react.
FIGURE 9. BIAS POWER ON RESET
FIGURE 10. CHARGE PUMP VOLTAGE
FIGURE 11. GATE TURN-OFF/ON (DIS)CHARGE CURRENT FIGURE 12. FAULT GATE TURN-OFF SINK CURRENT
Typical Performance Curves (Continued)
1.23
1.24
1.25
1.26
1.27
1.28
1.29
-40 -20 0 25 45 75 85 100 125
TEMPERATURE (°C)
DLY VTH (V)
DLY_ON Vth
DLY_OFF Vth
4.8
5.0
5.2
5.4
5.6
5.8
.
-40 -20 0 25 45 75 85 100 125
TEMPERATURE (°C)
Q-PUMP VOLTAGE (V)
V
DD
= 5V
V
DD
= 2.5V
9.4
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
-40 -20 0 25 45 75 85 100 125
TEMPERATURE (°C)
GATE CURRENT (µA)
I_GATE_OFF
I_GATE_ON
40
50
60
70
80
90
100
-40 -20 0 25 45 75 85 100 125
TEMPERATURE (°C)
FAULT GATE CURRENT (mA)
ISL8723, ISL8724
