10
FN6413.1
April 22, 2009
ISL8723, ISL8724
FIGURE 19. 4 UVLOs VALID, ENABLE HIGH TO SYSRST HIGH FIGURE 20. ENABLE LOW TO RESET AND SYSRST LOW
FIGURE 21. UVLO INVALID TO RESET
AND SYSRST LOW
Typical Performance Waveforms (Continued)
ENABLE
SYSRST
ENABLE
SYSRST
RESET
SYSRST
RESET
UVLO
11
FN6413.1
April 22, 2009
+2.5V1.5V+3.3V
+5V
C1
1µF
C2
0.01µF
0.022µF
OPEN
0.068µF
C3
C5
C4
C6
0.047µF
C8
0.01µF
C7
OPEN
C9
0.1µF
NC
SYSRST
GND
RESET
GATE_C
GATE_D
GATE_B
GATE_A
ISL8723IR
UVLO_A
DLY_OFF_BUVLO_D
UVLO_C
UVLO_B
DLY_OFF_D
DLY_OFF_C
DLY_ON_A
U1
DLY_ON_C
DLY_ON_D
DLY_ON_B
V
DD
ENABLE
3.01k
1.47k
4.99k
R12 R3
EN
R1
R4
R2
R6
7.681k 4.99k 6.98k 8.45k
12
17
14
20
22
9,11
R9
750
2
5
7
6
SYSRST
3
4
13
18
21
16
15
8
23
Q1A
4
5
3
2
Q1B
7
5
6
R9 10 R10 10 R13 10
R14
10
2
4
3
FDS6990S
FDS6990S
FDS6990S
8
6
FDS6990S
1
8
Q2B
DLY_OFF_A
R5
R11
10
1
1
24
2.26k
FIGURE 22. ISL8723EVAL1 BOARD SCHEMATIC
7
1
Q2A
19
D1
FIGURE 23. EVAL BOARD PHOTOGRAPH
ISL8723, ISL8724
12
FN6413.1
April 22, 2009
Application Implementations
Multiple Sequencer Implementations
In order to control the sequencing of more than 4 voltages in
applications where the integrity of these critical voltages must
be assured prior to sequencing, several of the ISL8723 or
ISL8724 devices can configured together to accomplish this.
Figure 24 shows a typical multi sequencer implementation;
note the common SYSRST
signal that asserts once all
monitored voltages are valid allowing the sequence to
initiate. The sequencing is straight forward across multiple
sequencers as all DLY_ON capacitors will simultaneously
start charging once all monitored voltages area valid and
~10ms after the common ENABLE input signal is delivered.
This allows the choice of capacitors to be related to each
other no different than using a single sequencer. When the
common enabling signal is deasserted, this configuration will
then execute the turn-off sequence across all sequencers as
programmed by the DLY_OFF capacitor values.
With all the SYSRST
pins bused together, once the on
sequence is complete, simultaneous shutdown upon any
UVLO input failure is assured as the SYSRST
output will pull
low, simultaneously turning off all GATE outputs.
TABLE 2. ISL872XSEQEVAL1 BOARD COMPONENT LISTING
COMPONENT
DESIGNATOR COMPONENT FUNCTION COMPONENT DESCRIPTION
U1 ISL8723, 4 Supply Sequencer Intersil, ISL8723IR 4 Supply Sequencer
Q1, Q2 Voltage Rail Switches FDS6990S or equivalent, Dual N-Channel MOSFET
R6 5V to UVLO_A Resistor for Divider String 8.45kΩ 1%, 0402
R11 UVLO_A to GND Resistor for Divider String 1.47kΩ 1%, 0402
R1 3.3V to UVLO_B Resistor for Divider String 7.68kΩ 1%, 0402
R12 UVLO_B to GND Resistor for Divider String 2.26kΩ 1%, 0402
R2 2.5V to UVLO_D Resistor for Divider String 6.98kΩ 1%, 0402
R3 UVLO_D to GND Resistor for Divider String 3.01kΩ 1%, 0402
R4 1.5V to UVLO_C Resistor for Divider String 4.99kΩ 1%, 0402
R5 UVLO_D to GND Resistor for Divider String 4.99kΩ 1%, 0402
R9 RESET LED Current Limiting Resistor 750Ω 10%, 0805
C5 5V turn-on Delay Capacitor A (~10ms) DNP, 0402
C9 5V turn-off Delay Capacitor A (~140ms) 0.1µF 10%, 6.3V, 0402
C2 3.3V turn-on Delay Capacitor B (~13ms) 0.01µF 10%, 6.3V, 0402
C8 3.3V turn-off Delay Capacitor B (~13ms) 0.01µF 10%, 6.3V, 0402
C3 2.5V turn-on Delay Capacitor D (~25ms) 0.022µF 10%, 6.3V, 0402
C7 2.5V turn-off Delay Capacitor D (0ms) DNP, 0402
C4 1.5V turn-on Delay Capacitor C (~100ms) 0.068µF 10%, 6.3V, 0402
C6 1.5V turn-off Delay Capacitor C (~60ms) 0.047µF 10%, 6.3V, 0402
C1 Decoupling Capacitor 1µF, 0805
D1 RESET Indicating LED 0805, SMD LEDs Red
R9 5V Load Resistor 10Ω 20%, 3W Carbon
R10 3.3V Load Resistor 10Ω 20%, 3W Carbon
R13 2.5V Load Resistor 10Ω 20%, 3W Carbon
R14 1.5V Load Resistor 10Ω 20%, 3W Carbon
Test Points Labeled as to Function
ISL8723, ISL8724

ISL8723EVAL1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Power Management IC Development Tools ISL8723 EVAL BRD 1
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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