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83948AYI-147LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
1©2016 Integrated Device Technology, Inc Revision D March 30, 2016
General Description
The 83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVT-
TL Fanout Buffer. The 83948I-147 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential input lev-
els. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to drive
50 series or parallel terminated transmission lines. The effective fa-
nout can be increased from 12 to 24 by utilizing the ability of the out-
puts to drive two series terminated lines.
The 83948I-147 is characterized at full 3.3V, full 2.5V or mixed 3.3V
core/2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the 83948I-147 ideal for those
clock distribution applications demanding well defined performance
and repeatability.
Features
• Twelve LVCMOS/LVTTL outputs
• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Output frequency: 350MHz
• Additive phase jitter, RMS: 0.14ps (typical)
• Output skew: 100ps (maximum), 3.3V±5%
• Part-to-part skew: 1ns (maximum), 3.3V±5%
• Operating supply modes:
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram Pin Assignment
83948I-147
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
1
0
D
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
CLK_EN
CLK_SEL
OE
LVCMOS_CLK
CLK
nCLK
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
Q11
V
DDO
Q10
GND
Q9
V
DDO
Q8
GND
Q0
V
DDO
Q1
GND
Q2
V
DDO
Q3
GND
83948I-147
Data Sheet
Low Skew, 1-to-1 Differential-
to-LVCMOS/ LVTTL Fanout Buffer
2©2016 Integrated Device Technology, Inc Revision D March 30, 2016
83948I-147 Data Sheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. Clock Select Function Table
Number Name Type Description
1 CLK_SEL Input Pullup
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
2
LVCMOS_CL
K
Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels.
3 CLK Input Pullup Non-inverting differential clock input.
4 nCLK Input Pulldown Inverting differential clock input.
5 CLK_EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels.
6 OE Input Pullup
Output enable pin. When LOW, outputs are in an High-impedance state.
when HIGH, outputs are active. LVCMOS/LVTTL interface levels.
7V
DD
Power Power supply pin.
8, 12, 16,
20, 24, 28, 32
GND Power Power supply ground.
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
Q11, Q10,
Q9, Q8, Q7,
Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
10, 14, 18,
22, 26, 30
V
DDO
Power Output supply pins.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation Capacitance
(per output)
12 pF
R
OUT
Output Impedance 5 7 12
Control
Input
Clock
0 CLK/nCLK inputs selected
1 LVCMOS_CLK input selected
3©2016 Integrated Device Technology, Inc Revision D March 30, 2016
83948I-147 Data Sheet
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Table 4B. Power Supply DC Characteristics, V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Inputs Outputs
Input to Output Mode PolarityCLK_SEL LVCMOS_CLK CLK nCLK Q[0:11]
0 – 0 1 LOW Differential to Single-Ended Non-Inverting
0 – 1 0 HIGH Differential to Single-Ended Non-Inverting
0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting
0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting
0 – Biased; NOTE 1 0 HIGH Single-Ended to Single-Ended Inverting
0 – Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting
1 0 – – LOW Single-Ended to Single-Ended Non-Inverting
1 1 – – HIGH Single-Ended to Single-Ended Non-Inverting
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
73.6C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 55 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 2.375 2.5 2.625 V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 52 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

83948AYI-147LFT

Mfr. #:
Buy 83948AYI-147LFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 12 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
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