7©2016 Integrated Device Technology, Inc Revision D March 30, 2016
83948I-147 Data Sheet
Table 5C. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation
Delay
CLK/nCLK; NOTE 1 ƒ 350MHz 2 4 ns
LVCMOS_CLK;
NOTE 2
ƒ 350MHz 2 4 ns
tjit
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range:
12kHz – 20MHz
0.14 1 ps
tsk(o) Output Skew; NOTE 3, 7
Measured on the Rising Edge
@ V
DDO
/2
100 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 7
Measured on the Rising Edge
@ V
DDO
/2
1ns
t
R
/ t
F
Output Rise/Fall Time 0.8V to 2V 0.1 1.0 ns
odc Output Duty Cycle ƒ 200MHz, Ref = CLK/nCLK 45 55 %
t
PZL,
t
PZH
Output Enable Time; NOTE 5 5ns
t
PLZ,
t
PHZ
Output Disable Time; NOTE 5 5ns
t
S
Clock Enable
Setup Time;
NOTE 6
CLK_EN to CLK/nCLK 1 ns
CLK_EN to
LVCMOS_CLK
0ns
t
H
Clock Enable
Hold Time;
NOTE 6
CLK/nCLK to CLK_EN 0 ns
LVCMOS_CLK to
CLK_EN
1ns
