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83948AYI-147LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4©2016 Integrated Device Technology, Inc Revision D March 30, 2016
83948I-147 Data Sheet
Table 4C. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Table 4D. DC Characteristics, T
A
= -40°C to 85°C
NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to V
DDO
/2. See Parameter Measurement section, Output
Load AC Test Circuit diagrams.
NOTE 2: V
IL
should not be less than -0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 55 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
LVCMOS V
DD
= 3.465V 2 V
DD
+ 0.3 V
LVCMOS V
DD
= 2.625V 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage
LVCMOS V
DD
= 3.465V -0.3 0.8 V
LVCMOS V
DD
= 2.625V -0.3 0.7 V
I
IN
Input Current V
IN
= V
DD
or V
IN
= 3.465V or 2.625V 300 µA
V
OH
Output High Voltage; NOTE 1
V
DDO
= 3.3V ± 5%
I
OH
= -24mA
2.4 V
V
DDO
= 2.5V ± 5%
I
OH
= -15mA
1.8 V
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 3.3V ± 5%
I
OL
= 24mA
0.55 V
V
DDO
= 3.3V ± 5%
I
OL
= 12mA
0.30 V
V
DDO
= 2.5V ± 5%
I
OL
= 15mA
0.6 V
V
PP
Peak-to-Peak Input
Voltage; NOTE 2
CLK/nCLK V
DD
= 3.465V or 2.625V 0.15 1.3 V
V
CMR
Common Mode
Input Voltage;
NOTE 2, 3
CLK/nCLK
V
DD
= 3.465V or 2.625V GND + 0.5 V
DD
– 0.85 V
5©2016 Integrated Device Technology, Inc Revision D March 30, 2016
83948I-147 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation
Delay
CLK/nCLK; NOTE 1 ƒ 350MHz 2 4 ns
LVCMOS_CLK;
NOTE 2
ƒ 350MHz 2 4 ns
tjit
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range:
12kHz – 20MHz
0.14 1 ps
tsk(o) Output Skew; NOTE 3, 7
Measured on the Rising Edge
@ V
DDO
/2
100 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 7
Measured on the Rising Edge
@ V
DDO
/2
1ns
t
R
/ t
F
Output Rise/Fall Time 0.8V to 2V 0.2 1.0 ns
odc Output Duty Cycle ƒ 150MHz, Ref = CLK/nCLK 45 50 55 %
t
PZL,
t
PZH
Output Enable Time; NOTE 5 5ns
t
PLZ,
t
PHZ
Output Disable Time; NOTE 5 5ns
t
S
Clock Enable
Setup Time;
NOTE 6
CLK_EN to CLK/nCLK 1 ns
CLK_EN to
LVCMOS_CLK
0ns
t
H
Clock Enable
Hold Time;
NOTE 6
CLK/nCLK to CLK_EN 0 ns
LVCMOS_CLK to
CLK_EN
1ns
6©2016 Integrated Device Technology, Inc Revision D March 30, 2016
83948I-147 Data Sheet
Table 5B. AC Characteristics, V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation
Delay
CLK/nCLK; NOTE 1 ƒ 350MHz 1.5 4.2 ns
LVCMOS_CLK;
NOTE 2
ƒ 350MHz 1.7 4.4 ns
tjit
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range:
12kHz – 20MHz
0.14 1 ps
tsk(o) Output Skew; NOTE 3, 7
Measured on the Rising Edge
@ V
DDO
/2
160 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 7
Measured on the Rising Edge
@ V
DDO
/2
2ns
t
R
/ t
F
Output Rise/Fall Time 0.6V to 1.8V 0.1 1.0 ns
odc Output Duty Cycle ƒ 150MHz, Ref = CLK/nCLK 40 60 %
t
PZL,
t
PZH
Output Enable Time; NOTE 5 5ns
t
PLZ,
t
PHZ
Output Disable Time; NOTE 5 5ns
t
S
Clock Enable
Setup Time;
NOTE 6
CLK_EN to CLK/nCLK 1 ns
CLK_EN to
LVCMOS_CLK
0ns
t
H
Clock Enable
Hold Time;
NOTE 6
CLK/nCLK to CLK_EN 0 ns
LVCMOS_CLK to
CLK_EN
1ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

83948AYI-147LFT

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Buy 83948AYI-147LFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 12 LVCMOS OUT BUFFER
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