PCF8566T/1,118 Datasheet PCF8566T/1,118, PCF8566P,112, PCF8566T/1,112 | P22-P24

Product data sheet Rev. 07 — 25 February 2009 22 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

• A master receiver must signal an end-of-data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

master receiver must leave the data line HIGH during the 9th pulse to not

acknowledge. The master will now generate a STOP condition.

8.1.4 PCF8566 I

C-bus controller

The PCF8566 acts as an I

C-bus slave receiver. It does not initiate I

C-bus transfers or

transmit data to an I

C-bus master receiver. The only data output from the PCF8566 are

the acknowledge signals of the selected devices. Device selection depends on the

C-bus slave address, the transferred command data and the hardware subaddress.

In single device application, the hardware subaddress inputs A0, A1 and A2 are normally

tied to V

which deﬁnes the hardware subaddress 0. In multiple device applications

A0, A1 and A2 are tied to V

or V

using a binary coding scheme so that no two

devices with a common I

C-bus slave address have the same hardware subaddress.

In the power-saving mode it is possible that the PCF8566 is not able to keep up with the

highest transmission rates when large amounts of display data are transmitted. If this

situation occurs, the PCF8566 forces the SCL line LOW until its internal operations are

completed. This is known as the clock synchronization feature of the I

C-bus and serves

to slow down fast transmitters. Data loss does not occur.

8.1.5 Input ﬁlter

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

8.2 I

C-bus protocol

Two I

C-bus 7 bit slave addresses (0111 110 and 0111 111) are reserved for the

PCF8566. The least signiﬁcant bit after the slave address is bit R/W. The PCF8566 is a

write-only device. It will not respond to a read access, so this bit should always be logic 0.

The second bit of the slave address is deﬁned by the level tied at input SA0.

Fig 15. Acknowledgement on the I

C-bus

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Product data sheet Rev. 07 — 25 February 2009 23 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

Two displays controlled by PCF8566 can be recognized on the same I

C-bus which

allows:

• Up to 16 PCF8566s on the same I

C-bus for very large LCD applications (see

Section 13)

• The use of two types of LCD multiplex on the same I

C-bus

The I

C-bus protocol is shown in Figure 17. The sequence is initiated with a START

condition (S) from the I

C-bus master which is followed by one of the PCF8566 slave

addresses. All PCF8566s with the same SA0 level acknowledge in parallel to the slave

address. All PCF8566s with the alternative SA0 level ignore the whole I

C-bus transfer.

After acknowledgement, one or more command bytes (m) follow which deﬁne the status of

the addressed PCF8566s. The last command byte is tagged with a cleared most

signiﬁcant bit, the continuation bit C. The command bytes are also acknowledged by all

addressed PCF8566s on the bus.

After the last command byte, a series of display data bytes (n) may follow. These display

bytes are stored in the display RAM at the address speciﬁed by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data is directed to the intended PCF8566 device.

The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed

PCF8566. After the last display byte, the I

C-bus master issues a STOP condition (P).

Fig 16. Slave address structure

Fig 17. I

C-bus protocol

001aai455

011111 0

slave address

1 byte

R/W

mgg390

S 011111 0AC

COMMAND

A PADISPLAY DATA

slave address

acknowledge by

all addressed

PCF8566s

acknowledge

by A0, A1 and A2

selected

PCF8566 only

m ≥ 1 byte(s) n > 0 byte(s)1 byte

update data pointers

and if necessary,

subaddress counter

R/W

Product data sheet Rev. 07 — 25 February 2009 24 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

8.3 Command decoder

The command decoder identiﬁes command bytes that arrive on the I

C-bus. All available

commands carry a continuation bit C in their most signiﬁcant bit position as shown in

Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will

also represent a command. If this bit is reset, it indicates that the command byte is the last

in the transfer. Further bytes will be regarded as display data.

The ﬁve commands available to the PCF8566 are deﬁned in Table 8.

8.3.1 Mode set command

(1) C = 0; last command.

(2) C = 1; commands continue.

Fig 18. General format of byte command

msa833

REST OF OPCODE

MSB LSB

Table 8. Deﬁnition of PCF8566 commands

Command Opcode Reference Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mode set C 1 0 LP E B M1 M0

Section 8.3.1 deﬁnes LCD drive mode, LCD bias

conﬁguration, display status and

power dissipation mode

Load data

pointer

C 0 0 P4P3P2P1P0

Section 8.3.2 data pointer to deﬁne one of 24

display RAM addresses

Device select C 1100A2A1A0

Section 8.3.3 deﬁne one of eight hardware

subaddresses

Bank select C 11110I O

Section 8.3.4 bit I: deﬁnes input bank selection

(storage of arriving display data);

bit O: deﬁnes output bank selection

(retrieval of LCD display data)

Blink C 1110ABF1BF0

Section 8.3.5 deﬁnes the blink frequency and blink

mode

Table 9. LCD drive mode command bit description

LCD drive mode Bit

Drive mode Backplane M1 M0

static BP0 0 1

1:2 BP0, BP1 1 0

1:3 BP0, BP1. BP2 1 1

1:4 BP0, BP1. BP2, BP3 0 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48

PCF8566T/1,118

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Manufacturer:

NXP Semiconductors

Description:

LCD Drivers LCD DVR UNVRSL LOW-MUX

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PCF8566T/1,118

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