PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 25 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
[1] The possibility to disable the display allows implementation of blinking under external control.
8.3.2 Load data pointer command
8.3.3 Device select command
8.3.4 Bank select command
[1] The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.
Table 10. LCD bias configuration command bit description
LCD bias Bit B
1
3
bias 0
1
2
bias 1
Table 11. Display status command bit description
[1]
Display status Bit E
disabled (blank) 0
enabled 1
Table 12. Power dissipation mode command bit description
Display status Bit LP
normal mode 0
power saving mode 1
Table 13. Load data pointer command bit description
Description Bit
5 bit binary value, 0 to 23 P4 P3 P2 P1 P0
Table 14. Device select command bit description
Description Bit
3 bit binary value, 0 to 7 A2 A1 A0
Table 15. Bank select command
[1]
Bank Mode Bit Value
Static 1:2 MUX
Input bank
RAM bit 0 RAM bits 0 and 1 I 0
RAM bit 2 RAM bits 2 and 3 1
Output bank
RAM bit 0 RAM bits 0 and 1 O 0
RAM bit 2 RAM bits 2 and 3 1
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 26 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
8.3.5 Blink command
8.4 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF8566 and coordinates their effects. The controller
also loads display data into the display RAM as required by the storage order.
9. Internal circuitry
Table 16. Blink frequency command bit description
Blink frequency Bit
BF1 BF0
off 0 0
101
210
311
Table 17. Blink mode command bit description
Blink mode Bit A
Normal blinking 0
Alternate RAM bank blinking 1
Fig 19. Device protection diagram
001aai456
V
LCD
V
SS
SDA, SCL, SYNC,
CLK, OSC, A0 to A2,
SA0
V
DD
BP0 to BP3,
S0 to S23
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 27 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
10. Limiting values
[1] Values with respect to V
DD
.
[2] According to the NXP store and transport conditions (document
SNW-SQ-623
) the devices have to be
stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
[3] Pass level; Human Body Model (HBM) according to JESD22-A114.
[4] Pass level; Machine Model (MM), according to JESD22-A115.
[5] Pass level; latch-up testing, according to JESD78.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(V
LCD
) is on while the IC supply voltage (V
DD
) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, V
LCD
and V
DD
must be applied or removed together.
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 7.0 V
V
LCD
LCD supply voltage
[1]
0.5 7.0 V
V
I
input voltage on each of the pins SCL,
SDA, A0 to A2, OSC, CLK,
SYNC and SA0
0.5 7.0 V
V
O
output voltage on each of the pins S0 to S23
and BP0 to BP3
[1]
0.5 7.0 V
I
I
input current 20 +20 mA
I
O
output current 25 +25 mA
I
DD
supply current 50 +50 mA
I
SS
ground supply
current
50 +50 mA
I
DD(LCD)
LCD supply current 50 +50 mA
P
tot
total power
dissipation
per package - 400 mW
P
o
output power - 100 mW
T
stg
storage
temperature
[2]
65 +150 °C
V
esd
electrostatic
discharge voltage
HBM
[3]
- ±2000 V
MM
[4]
- ±200 V
I
lu
latch-up current
[5]
- 100 mA

PCF8566T/1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers LCD DVR UNVRSL LOW-MUX
Lifecycle:
New from this manufacturer.
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