MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
10 ______________________________________________________________________________________
Compensation
A compensation capacitor, C1, may be needed when
the DAC is used with a high-speed output amplifier.
The capacitor cancels the pole formed by the DAC’s
output capacitance and internal feedback resistance.
Its value depends on the type of op amp used, but typi-
cal values range from 10pF to 33pF. Too small a value
causes output ringing, while excess capacitance over-
damps the output. Minimize C1’s size and improve out-
put settling performance by keeping the PC board
trace as short as possible and stray capacitance at
I
OUT
as small as possible.
Bypassing
Place a 1µF bypass capacitor, in parallel with a 0.01µF
ceramic capacitor, as close to the DAC’s V
DD
and GND
pins as possible. Use a 1µF tantalum bypass capacitor
to optimize high-frequency noise rejection. Place a
4.7µF decoupling capacitor at V
SS
to minimize the DAC
output leakage current.
The MX7534/MX7535 have high-impedance digital
inputs. To minimize noise pickup, connect them to
either V
DD
or GND terminals when not in use. Connect
active inputs to V
DD
or GND through high-value resis-
tors (1M) to prevent static charge accumulation if
these pins are left floating, as might be the case when
a circuit card is left unconnected.
Op-Amp Selection
Input offset voltage (V
OS
), input bias current (I
B
), and
offset voltage drift (TC V
OS
) are three key parameters in
determining the choice of a suitable amplifier. To main-
tain specified accuracy with V
REF
of 10V, V
OS
should
be less than 30µV and I
B
should be less than 2nA.
Open-loop gain should be greater than 340,000.
Maxim’s MAX400 has low V
OS
(10µV max), low I
B
(2nA), and low TC V
OS
(0.3µV/°C max). This op amp
can be used without requiring any adjustments. For
OP AMP
INPUT OFFSET
VOLTAGE (V
OS
)
INPUT BIAS
CURRENT (I
B
)
OFFSET VOLTAGE
DRIFT (TC V
OS
)
SETTLING
TO 0.003% FS
MAX400 10µV 2nA 0.3µV/°C 50µs
Maxim OP07 25µV 2nA 0.6µV/°C 50µs
AD554L* 500µV 25pA 5µV/°C 5µs
HA2620* 4mV 35nA 20µV/°C 0.8µs
Table 5. Amplifier Performance Comparisons
* AD544L is an Analog Devices part; HA2620 is a Harris Semiconductor part.
R4
33
R3
100
INPUT
DATA
SIGNAL
GROUND
A1
A2
7–14
620
5
4
3
2
191
C1
33pF
V
DD
V
DD
R
L
V
SS
MX7534
REF RFB
IOUT
AGNDS
AGNDF
DGNDD7–D0
+
+
V
IN
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
V
O
Figure 6a. Unipolar Binary Operation with Forced Ground
R2
10
R1
20
INPUT
DATA
SIGNAL
GROUND
ANALOG
GROUND
A1
A2
8–21
7
27
6
5
4
32621
C1
33pF
V
DD
V
DD
R
L
V
SS
MX7535
REFF REFS RFB
IOUT
AGNDS
AGNDF
DGNDD13–D0
+
+
VOLTAGE
REFERENCE
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
V
O
Figure 6b. Unipolar Binary Operation with Forced Ground for
Remote Load
medium-frequency applications, the OP27 is recom-
mended. For higher-frequency applications, the HA-
2620 is recommended. However, these op amps
require external offset adjustment (Table 5).
________Microprocessor Interfacing
8086 with MX7535
The MX7534/MX7535 interface to both 8-bit and 16-bit
processors. Figure 9a shows the 8086 16-bit processor
interfacing to a single MX7535. In this setup, the double-
buffering feature of the DAC is not used. AD0–AD13 of
the 16-bit data bus are connected to the DAC data bus
(D0–D13). The 14-bit word is written to the DAC in one
MOV instruction, and the analog output responds imme-
diately. In this example, the DAC address is D000. Table
6a shows a software routine for Figure 9a.
In a multiple DAC system, the double buffering of the
DAC chips allows the user to simultaneously update all
DACs. In Figure 10, a 14-bit word is loaded to each of
the DAC’s input registers in sequence. Then, with one
instruction to the appropriate address, CS4 (i.e., LDAC)
is brought low, updating all the DACs simultaneously.
8086 with MX7534
Figure 9b shows an interface circuit to a 16-bit micro-
processor. The bottom 8 bits (AD0–AD7) of the 16-bit
data bus are connected to the DAC data bus. The
14-bit word is loaded in two bytes, using the MOV
instruction. A further MOV loads the DAC register and
causes the analog data to appear at the converter out-
put. For the example given here, the appropriate DAC
register addresses are D002, D004, and D006. Table
6b shows the program for loading the DAC.
8085A with MX7534
A typical interface circuit is shown in Figure 9c. The
DAC is treated as four memory locations addressed by
A0 and A1. In standard operation, three of these memo-
ry locations are used. Table 6c shows a sample pro-
gram for loading the DAC with a 14-bit word. The
MX7534 has address locations 3000–3003.
The six MSBs are written into location 3001, and eight
LSBs are written to 3002. Then, with a write instruction to
3003, the full 14-bit word is loaded to the DAC register.
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
______________________________________________________________________________________ 11
R
L
INPUT
DATA
A3
8–21
7
27
6
5
4
3
2
261
C1
33pF
V
DD
V
0
V
SS
V
DD
MX7535
REFF REFS RFB
IOUT
AGNDS
AGNDF
DGNDD13–D0
+
A2
+
A1
+
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
Figure 7. Driving the MX7535 with a Remote Voltage Reference
AGND
DGND
REF
PIN 1 AD544*
OUTPUT
V
SS
V
DD
C1 LOCATION
V+
V-
NOTE:
LAYOUT IS FOR DOUBLE-SIDED
PCB. BOLD LINE INDICATES
TRACK ON COMPONENT SIDE.
*AD544 IS AN ANALOG DEVICES PART.
PIN 1 MX7534
Figure 8. Suggested Layout for MX7534 Incorporating Output
Amplifier
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
12 ______________________________________________________________________________________
MC68000 with MX7535
Figure 11a shows an interface diagram. The following
routine writes data to the DAC input registers and then
outputs the data via the DAC register:
01000 MOVE.W #W,D0 DAC data, W, loaded
into Data Register 0.
MOVE.W D0,$E000 Data W transferred
between D0 and DAC
Register.
MOVE.B #228,D7 Control returned to the
System.
TRAP #14 Monitor Program
MC68000 with MX7534
Figure 11b shows the MC68000 interface diagram. The
following routine writes data to the DAC input registers
and then outputs the data via the DAC register:
.A2 E003 Address Register 2
loaded with E003.
01000 MOVE.W #W,D0 DAC data, W, loaded
into Data Register 0.
MOVEP.W D0,$0000
(A2)
Data W transferred
between D0 and the
DAC’s Input Register.
High-ordered byte trans-
ferred first. Memory
address specified using
the address register
indirect plus displace-
ment addressing mode.
Address used here
(E003) is odd, so data is
transferred on the low-
order half of the data
bus (D0–D7).
MOVE.W D0,$E006 This instruction provides
appropriate signals to
transfer data W from
the DAC Input Register
to the DAC Register,
which controls the R-2R
ladder switches.
MOVE.B #228,D7 Control returned to the
System.
TRAP #14 Monitor Program
Since this interfacing system uses only the lower half of
the data bus, it is also suitable for use with the
MC68008, which provides the user with an 8-bit data
bus instead of the MC68000’s 16-bit bus.
ADDRESS
DECODE
LATCH
ADDRESS BUS
CS
WR
D0–D7
A1 A0
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
AE
A8–A15
8085A
DATA BUS
AD0–AD7
WR
Figure 9c. MX7534—8085A Interface Circuit
ADDRESS
DECODE
16-BIT
LATCH
ADDRESS BUS
DATA BUS
ALE
8086
CS
WR
D0–D7
A2
A1 A0
A1
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
ADDRESS BUS
AD0–AD15
WR
Figure 9b. MX7534—8086 Interface Circuit
ADDRESS
DECODE
16-BIT
LATCH
ADDRESS BUS
DATA BUS
ALE
8086
LDAC
CSLSB
CSMSB
WR
D0–D13
AD13
AD0
MX7535*
*SOME CIRCUITRY OMITTED FOR CLARITY
AD0–AD15
WR
Figure 9a. MX7535—8086 Interface Circuit

MX7534KP+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 14-Bit Precision DAC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union