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MX7534KP+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
_______________________________________________________________________________________ 7
Zero-Offset Adjustment
(Figures 4a and 4b)
1) Load the DAC register with all 0s.
2) Adjust the offset of amplifier A1 so that V
0
(see fig-
ure) is at a minimum (i.e., ≤ 30µV).
Gain Adjustment
(Figures 4a and 4b)
1) Load the DAC register with all 1s.
2) Trim potentiometer R1 so that V
OUT
= -V
IN
(
16383
)
16384
In fixed-reference applications, adjust full scale by
omitting R1 and R2 and trimming the reference voltage
magnitude. In many applications, the excellent Gain
Tempco and Gain Error specifications eliminate the
need for gain adjustment. However, if trims are
required and the DAC is to operate over a wide temper-
ature range, use low-tempco (>300ppm/°C) resistors.
Bipolar Operation
(4-Quadrant Multiplication)
Bipolar or 4-quadrant operation is shown in Figures 5a
and 5b. This configuration provides for offset binary
coding. Table 4 shows DAC codes and the corre-
sponding analog outputs for Figures 5a and 5b. With
the DAC loaded to 10 0000 0000 0000, either adjust R1
for V
OUT
= 0V, or omit R1 and R2 and adjust the ratio of
R5 and R6 for V
OUT
= 0V. Adjust the amplitude of V
IN
or vary the value of R7 for full-scale trimming.
Resistors R5, R6, and R7 must be matched to 0.003%.
Mismatch of R5 and R6 causes both offset and full-
scale errors. For wide temperature range operation,
use resistors of the same material so that their tempera-
ture coefficients match and track.
2R 2R
G F E D C B A S10 S9 S0
2R 2R 2R 2R 2R 2R 2R
R
RR
2R2R
R/4
RFB
IOUT
AGNDS
AGNDF
*NOTE: VALID FOR MX7535. IN MX7534, 0REFS AND 0REFF ARE REPLACED BY ONE PIN: REF.
REFS*
REFF*
R/4
+
–
AGNDS
AGNDF
IOUT
RFB
I
LEAKAGE
g(V
REF
, N) C
OUT
R
O
Figure 2. Simplified Circuit Diagram
Figure 3. Equivalent Analog Output Circuit
Table 1. MX7534 Logic States
A1 A2 FUNCTION
X 1 X X Device not selected (Note 1)
1 X X X No data transfer
0000
DAC loaded directly from
Data Bus (Note 2)
0001
MS Input Register loaded
from Data Bus
0010
LS Input Register loaded
from Data Bus
0011
DAC Register loaded from
Input Registers
Note 1: X = Don’t Care.
Note 2: When A1 = 0 and A0 = 0, all DAC registers are trans-
parent. By placing all 0s or all 1s on the data inputs, the
user can load the DAC to zero or full-scale output in
one write operation. This simplifies system calibration.
MX7534/MX7535
Grounding Considerations
Since IOUT and the output amplifier noninverting input
are sensitive to offset voltages, connect nodes that
must be grounded directly to a single-point ground
through a separate, very-low-resistance path. Note that
the output currents at IOUT and AGNDF vary with input
code and create code-dependent error if these termi-
nals are connected to ground (or a virtual ground)
through a resistive path.
To obtain high accuracy, it is important to use a proper
grounding technique. The two AGND pins (AGNDF‚
AGNDS) provide flexibility in this respect. In Figures 4a
and 4b, AGNDS and AGNDF are shorted together
externally and an extra op amp, A2, is not used.
Voltage-drops due to bond-wire resistance are not
compensated for in this circuit; this could create a lin-
earity error of approximately 0.1LSB due to bond-wire
resistance alone. This can be eliminated by using the
circuits shown in Figures 6a and 6b, where A2 main-
tains AGNDS at signal ground potential. By using
force/sense techniques, all switch contacts on the DAC
are kept at exactly the same potential, and any error
caused by bond-wire resistance is eliminated.
Figure 7 shows a remote voltage reference driving the
MX7535. Op amps A2 and A3 compensate for voltage
drops along the reference input line and analog
ground line.
Figure 8 shows a printed circuit board (PCB) layout with
a single output amplifier for the MX7534. The input to
REF (Pin 1) is shielded to reduce AC feedthrough, while
the digital inputs are shielded to minimize digital
feedthrough. The traces connecting IOUT and AGNDS
to the inverting and noninverting op amp inputs are
kept as short as possible. Gain trim components, R3
and R4, are omitted.
Zero-Offset Adjustment
(Figures 6a and 6b)
1) Load DAC register with all 0s.
2) Adjust offset of amplifier A2 for minimum potential at
AGNDS. This potential should be ≤30µV with respect
to signal ground.
3) Adjust A1’s offset so that V
OUT
is at a minimum
(i.e., ≤30µV).
Microprocessor-Compatible,
14-Bit DACs
8 _______________________________________________________________________________________
Table 2. Unipolar Binary Code Table
BINARY NUMBER IN
DAC REGISTER
ANALOG OUTPUT
(V
OUT)
MSB LSB
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
-V
IN
(
16383
)
16384
-V
IN
(
8192
)
= -
1
V
IN
16384 2
-V
IN
(
1
)
16384
0V
R1
100Ω
R2
33Ω
INPUT
DATA
ANALOG
GROUND
A0
A1
A1
7–14
CS
WR
16
620
5
4
3
2191
C1
33pF
V
DD
V
IN
V
SS
MX7534
REF RFB
IOUT
AGNDS
AGNDF
DGND
D7–D0
15
18
17
V
O
R1
20Ω
R2
10Ω
INPUT
DATA
ANALOG
GROUND
LDAC
A1
CSMSB
8–21
CSLSB
WR
23
727
6
5
4
32261
C1
33pF
V
DD
V
IN
V
SS
MX7535
REFF
REFS
RFB
IOUT
AGNDS
AGNDF
DGNDD13–DO
22
25
24
V
O
Figure 4a. Unipolar Binary Operation
Figure 4b. Unipolar Binary Operation
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
_______________________________________________________________________________________ 9
Gain Adjustment
(Figures 6a and 6b)
1) Load DAC register with all 1s.
2) Trim potentiometer R3 so that V
OUT
= -
(
16383
)
V
IN
16384
Low-Leakage Configuration
Leakage current in the DAC flowing into the I
OUT
line
can cause gain, linearity, and offset errors. Leakage is
worse at high temperatures.
Negatively bias V
SS
for a high-temperature, low-leakage
configuration.
Dynamic Considerations
In static or DC applications, the output amplifier’s AC
characteristics are not critical. In higher-speed applica-
tions, where either the reference input is an AC signal
or the DAC output must quickly settle to a new pro-
grammed value, the output op amp’s AC parameters
must be considered.
Another error source in dynamic applications is the par-
asitic signal coupling from the REF terminal to I
OUT
.
This is normally a function of board layout and lead-to-
lead package capacitance. Signals can also be inject-
ed into the DAC outputs when the digital inputs are
switched. This digital feedthrough depends on circuit-
board layout and on-chip capacitive coupling. Minimize
layout-induced feedthrough with guard traces between
digital inputs, REF, and DAC outputs.
R1
100Ω
R2, 33Ω
R6
20k
R7
20k
R5 10k
R8, 5k,10%
INPUT
DATA
ANALOG
GROUND
A0
A1
A2
A1
7–14
WR
CS
16
620
5
4
3
2191
C1
33pF
V
IN
V
DD
V
SS
MX7534
REF RFB
IOUT
AGNDS
AGNDF
DGNDD7–D0
15
18
17
+
+
V
O
Figure 5a. Bipolar Operation
R1
20Ω
R2 10Ω
R6
20k
R7
20k
R5
10k
R8, 5k,10%
INPUT
DATA
ANALOG
GROUND
LDAC
A1
A2
CSMSB
8–21
WR
CSLSB
23
7
27
6
5
4
3
2
261
C1
33pF
V
IN
V
DD
V
SS
MX7535
REFF REFS RFB
IOUT
AGNDS
AGNDF
DGNDD13–D0
22
25
24
+
+
V
O
Figure 5b. Bipolar Operation
FUNCTION
0 1 1 0 Load MS Input Register
1 0 1 0 Load LS Input Register
0010
Load LS and MS Input
Registers
110X
Load DAC Register
from Input Register
0000
All registers are
transparent.
1 1 1 X No operation
X X 1 1 No operation
Table 3. MX7535 Logic States
Table 4. Offset Binary Bipolar Code Table
BINARY NUMBER IN
DAC REGISTER
Analog Output
(V
OUT)
MSB LSB
11 1111 1111 1111
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
+V
IN
(
8191
)
8192
+V
IN
(
1
)
8192
0
-V
IN
(
1
)
8192
-V
IN
(
8192
)
= -V
IN
8192
Note: X = Don’t Care.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MX7534KP+

Mfr. #:
Buy MX7534KP+
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 14-Bit Precision DAC
Lifecycle:
New from this manufacturer.
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