Z80 with MX7534/MX7535
Figure 12a is an interface circuit for the Z80, using the
MX7535. This is an example of an 8-bit processor inter-
face for these DACs. Figure 12b shows the schematic
for the MX7534.
MC6809 with MX7534
Figure 13a shows an interface circuit that enables the
MX7534 to be programmed using the MC6809 8-bit
microprocessor. Use the 16-bit D accumulator to simplify
data transfer. The two key processor instructions are:
LDD Load D accumulator from memory
STD Store D accumulator to memory
MC6502 with MX7534
Figure 13b shows an interface diagram for the MC6502
using the MX7534.
________________Digital Feedthrough
In the interface diagrams shown in Figures 9–13, the
digital inputs of the DAC are directly connected to the
microprocessor bus. Even when the device is not
selected, activity on the bus can feed through on the
DAC output through package capacitance and appear
as noise. To minimize noise, isolate the DACs from the
digital bus, as shown in Figures 14a and 14b.
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
______________________________________________________________________________________ 13
ASSUME DS:DACLOAD,CS:DACLOAD
DACLOAD SEGMENT AT 000
00
02
04
07
0B
0E
8CC9
8ED9
BF00D0
C705“YZWX”
EA0000
00FF
MOV CX,CS
MOVDS,CX
MOVDI,#D000
MOV MEM,#YZWX
:DEFINE DATA SEGMENT REGISTER EQUAL
:TO CODE SEGMENT REGISTER
:LOAD DI WITH D000
:DAC LOADED WITH WXYZ
:CONTROL IS RETURNED TO THE MONITOR PROGRAM
ASSUME DS:DACLOAD,CS:DACLOAD
DACLOAD SEGMENT AT 000
00
02
04
07
0A
0B
0C
0F
10
11
14
8CC9
8ED9
BF02D0
C605“MS”
47
47
C605“LS”
47
47
C60500
EA0000
MOV CX,CS
MOVDS,CX
MOVDI.#D002
MOV MEM,#“MS”
INC DI
INC DI
MOV MEM,#“LS”
INC DI
INC DI
MOV MEM,#00
JMP MEM
:DEFINE DATA SEGMENT REGISTER EQUAL
:TO CODE SEGMENT REGISTER
:LOAD DI WITH D002
:DAC LOADED WITH “MS”
:LS INPUT REGISTER LOADED WITH “LS”
:CONTENT OF INPUT REGISTERS ARE LOADED TO THE DAC REGISTER
:CONTROL IS RETURNED TO THE MONITOR PROGRAM
Table 6a. Sample Program for Loading the MX7535
Table 6b. Sample Program for Loading the MX7534 from 8086
2000
01
02
03
04
05
06
07
08
09
0A
0B
0C
200D
26
30
2E
01
3E
“MS”
77
2C
3E
“LS”
77
2C
77
CF
MVIH,#30
MVIL,#01
MVIA,#“MS”
MOV M,A
INR L
MVI A#“LS”
MOV M,A
INR L
MOV M,A
RST I
Table 6c. Sample Program for Loading
the MX7534 from 8085A
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
14 ______________________________________________________________________________________
ADDRESS
DECODE
ADDRESS BUS
DATA BUS
AS
DTACK
A1–A23
MC68000
LDAC
CSLSB
CSMSB
WR
D0–D13
D0–D15
MX7535*
*SOME CIRCUITRY OMITTED FOR CLARITY
R/W
Figure 11a. MX7535—MC68000 Interface
ADDRESS
DECODE
ADDRESS BUS
DATA BUS
AS
DTACK
A1–A23
A1A0
D0–D7
A2A1
MC68000
CS
WR
D0–D7
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
R/W
Figure 11b. MX7534—MC68000 Interface
CSMSB
WR
D0–D13
LDAC
CSLSB
ADDRESS
DECODE
16-BIT
LATCH
ADDRESS BUS
CSMSB
CSLSB
LDAC
WR
CS4
CS2
CS1
D0–D13
D0–D13
MX7535*
MX7535*
MX7535*
*SOME CIRCUITRY OMITTED FOR CLARITY
ALE
8086
AD0–AD15
WR
CSMSB
CSLSB
LDAC
WR
DATA BUS
CS3
Figure 10. MX7535—8086 Interface: Multiple DAC Systems
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
______________________________________________________________________________________ 15
ADDRESS
DECODE
CS
WR
D0–D7
A0 A1
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
ADDRESS BUS
A0–A15
MC6809
D0–D7
Q
E
R/W
DATA BUS
Figure 13a. MX7534—MC6809 Interface Circuit
ADDRESS
DECODE
ADDRESS BUS
CS
WR
D0–D7
A0 A1
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
ADDRESS BUS
A0–A15
6502
D0–D7
R/W
2
DATA BUS
Figure 13b. MX7534—6502 Interface
EN
QUAD LATCH
EN
QUAD LATCH
EN
QUAD LATCH
ADDRESS
DECODE
MICRO-
PROCESSOR
SYSTEM
A0–A15
WR
A0
A1
CS
A0 A1
D0–D7
D0–D7
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
WR
Figure 14a. MX7534—Interface Circuit Using Latches to
Minimize Digital Feedthrough
ADDRESS
DECODE
EN
16-BIT
LATCH
CSMSB
WR
D0–D13
MX7535*
*SOME CIRCUITRY OMITTED FOR CLARITY
CSLSB
LDAC
A0–A15
MICRO-
PROCESSOR
SYSTEM
D0–D15
WR
Figure 14b. MX7535—Interface Circuit Using Latches to
Minimize Digital Feedthrough
ADDRESS
DECODE
ADDRESS BUS
DATA BUS
MREQ
Z80
A0–A15
LDAC
CSMSB
CSLSB
WR
D0–D7
D8–D13
D8–D7
MX7535*
*SOME CIRCUITRY OMITTED FOR CLARITY
WR
Figure 12a. MX7535—Z80 Interface
ADDRESS
DECODE
CS
WR
D0–D7
A0 A1
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
ADDRESS BUS
A0–A15
Z80
D0–D7
WR
MREQ
DATA BUS
Figure 12b. MX7534—Z80 Interface

MX7534KP+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 14-Bit Precision DAC
Lifecycle:
New from this manufacturer.
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