AD8352ACPZ-R7 Datasheet AD8352ACPZ-R7, AD8352-EVALZ | P13-P15

AD8352

Rev. B | Page 12 of 20

0 800

(Ω)

GAIN (dB)

100 200 300 400 500 600 700

05728-028

Figure 24. Gain vs. R

, R

= 1 kΩ

(pF)

GAIN (dB)

0.1 0.2 0.3 0.4

05728-029

Figure 25. Gain vs. C

, R

= 1 kΩ

SINGLE-ENDED INPUT OPERATION

The AD8352 can be configured as a single-ended-to-differential

amplifier, as shown in Figure 26. To balance the outputs when

driving the VIP input, an external resistor (R

) of 200 Ω is added

between VIP and RGN. See Equation 2 to determine the single-

ended input gain (A

V Single-Ended

) for a given R

or R

430)53()5(

500

⎟

⎠

⎞

⎜

⎝

⎛

+++

−

EndedSingleV

(2)

where

is the single-ended load.

is the gain setting resistor.

Figure 27 plots gain vs. R

for 200 Ω and 1 kΩ loads. Table 7

and Table 8 show the values of C

and R

required (for 180 MHz

broadband, third-order, single tone optimization) for 200 Ω and

1 kΩ loads, respectively. This single-ended configuration provides

−3 dB bandwidths similar to input differential drive. Figure 28

through Figure 31 show distortion levels at a gain of 12 dB for

both 200 Ω and 1 kΩ loads. Gains from 3 dB to 18 dB, using

optimized C

and R

values, obtain similar distortion levels.

25Ω

65Ω

50Ω

0.1µF

RGP

RGN

AD8352

VIP

200Ω

05728-024

Figure 26. Single-Ended Schematic

1 10k

(Ω)

GAIN (dB)

10 100 1k

GAIN, R

=1kΩ

GAIN, R

=200Ω

05728-020

Figure 27. Gain vs. R

–

–110

FREQUENCY (MHz)

HD2 (dBc)

10 70 140 190 240

–70

–80

–90

–100

2V p-p OUT

1V p-p OUT

05728-021

Figure 28. Single-Ended, Second-Order Harmonic Distortion (HD2) vs.

Frequency, 200 Ω Load

AD8352

Rev. B | Page 13 of 20

This broadband optimization was also performed at 180 MHz.

As with differential input drive, the resulting distortion levels

at lower frequencies are based on the C

and R

specified in

Table 7 and Table 8. As with differential input drive, relative

third-order reduction improvement at frequencies below

140 MHz is realized with proper selection of C

and R

–

–110

FREQUENCY (MHz)

HD3 (dBc)

10 70 140 190 240

–70

–80

–90

–100

2V p-p OUT

1V p-p OUT

05728-022

Figure 29. Single-Ended, Third-Order Harmonic Distortion (HD3) vs.

Frequency, 200 Ω Load

–

–110

FREQUENCY (MHz)

HD2 (dBc)

10 70 140 190 240

–70

–80

–90

–100

1V p-p OUT

2V p-p OUT

05728-023

Figure 30. Single-Ended, Second-Order Harmonic Distortion (HD2) vs.

Frequency, 1 kΩ Load

–

–110

FREQUENCY (MHz)

HD3 (dBc)

10 70 140 190 240

–70

–80

–90

–100

1V p-p OUT

2V p-p OUT

05728-025

Figure 31. Single-Ended, Third-Order Harmonic Distortion (HD3) vs.

Frequency, 1 kΩ Load

Table 7. Distortion Cancellation Selection Components

and C

) for Required Gain, 200 Ω Load

(dB) R

(Ω) C

(pF) R

(kΩ)

3 4.3 k Open 4.3

6 540 Open 4.3

9 220 0.1 4.3

12 120 0.3 4.3

15 68 0.6 4.3

18 43 0.9 4.3

Table 8. Distortion Cancellation Selection Components

and C

) for Required Gain, 1 kΩ Load

(dB) R

(Ω) C

(pF) R

(kΩ)

6 3 k Open 4.3

9 470 Open 4.3

12 210 0.2 4.3

15 120 0.3 4.3

18 68 0.5 4.3

NARROW-BAND, THIRD-ORDER

INTERMODULATION CANCELLATION

Broadband single tone, third-order harmonic optimization does

not necessarily result in optimum (minimum) two tone, third-

order intermodulation levels. The specified values for C

and

in Table 5 and Tabl e 6 were determined for minimizing

broadband, single tone third-order levels.

Due to phase-related distortion coefficients, optimizing single

tone third-order distortion does not result in optimum in-band

(2f

− f

and 2f

− f

), third-order distortion levels. By proper

selection of C

(using a fixed 4.3 kΩ R

), IP3s of better than

45 dBm are achieved. This results in degraded out-of-band,

third-order frequencies (f

+ 2f

, f

+ 2f

, 3f

and 3f

). Thus, careful

frequency planning is required to determine the trade-offs.

Figure 32 shows narrow-band (2 MHz spacing) OIP3 levels

optimized at 32 MHz, 70 MHz, 100 MHz, and 180 MHz using

the C

values specified in Figure 33. These four data points (the

value and associated OIP3 levels) are extrapolated to provide

close estimates of OIP3 levels for any specific frequency between

30 MHz and 180 MHz. For frequencies below ~140 MHz, narrow-

band tuning of OIP3 results in relatively higher OIP3s (vs. the

broadband results shown in Table 2 of the specifications). Though

not shown, frequencies below 30 MHz also result in improved

OIP3s when using proper values for C

AD8352

Rev. B | Page 14 of 20

0 200

FREQUENCY (MHz)

OIP3 (dBm)

50 100 150

05728-030

= 200Ω

= 4.3kΩ

= 0.3pF

6dB

10dB

15dB

18dB

Figure 32. Third-Order Intermodulation Distortion, OIP3 vs.

Frequency for Various Gain Settings

6.0

30 190

FREQUENCY (MHz)

(pF)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

50 70 90 110 130 150 170

05728-031

= 200Ω

= 4.3kΩ

6dB

10dB

15dB

18dB

Figure 33. Narrow-Band C

vs. Frequency for Various Gain Settings

HIGH PERFORMANCE ADC DRIVING

The AD8352 provides the gain, isolation, and balanced low

distortion output levels for efficiently driving wideband ADCs

such as the AD9445.

Figure 34 and Figure 35 (single and differential input drive)

illustrate the typical front-end circuit interface for the AD8352

differentially driving the AD9445 14-bit ADC at 105 MSPS. The

AD8352, when used in the single-ended configuration, shows little

or no degradation in overall third-order harmonic performance

(vs. differential drive). See the Single-Ended Input Operation

section. The 100 MHz FFT plots shown in Figure 36 and Figure 37

display the results for the differential configuration. Though not

shown, the single-ended, third-order levels are similar.

The 50 Ω resistor shown in Figure 34 provides a 50 Ω differential

input impedance to the source for matching considerations.

When the driver is less than one eighth of the wavelength from

the AD8352, impedance matching is not required thereby negating

the need for this termination resistor. The output 24 Ω resistors

provide isolation from the analog-to-digital input.

Refer to the Layout and Transmission Line Effects section for

more information. The circuit in Figure 35 represents a single-

ended input to differential output configuration for driving the

AD9445. In this case, the input 50 Ω resistor with R

(typically

200 Ω) provide the input impedance match for a 50 Ω system.

Again, if input reflections are minimal, this impedance match is

not required. A fixed 200 Ω resistor (R

) is required to balance

the output voltages that are required for second-order distortion

cancellation. R

is the gain setting resistor for the AD8352 with

the R

and C

components providing distortion cancellation.

The AD9445 presents approximately 2 kΩ in parallel with

5 pF/differential load to the AD8352 and requires a 2.0 V p-p

differential signal (V

REF

= 1 V) between VIN+ and VIN− for a

full-scale output operation.

These AD8352 simplified circuits provide the gain, isolation,

and distortion performance necessary for efficiently driving

high linearity converters, such as the AD9445. This device also

provides balanced outputs whether driven differentially or single-

ended, thereby maintaining excellent second-order distortion

levels. However, at frequencies above ~100 MHz, due to phase-

related errors, single-ended, second-order distortion is relatively

higher. The output of the amplifier is ac-coupled to allow for an

optimum common-mode setting at the ADC input. Input ac

coupling can be required if the source also requires a common-

mode voltage that is outside the optimum range of the AD8352.

A VCM common-mode pin is provided on the AD8352 that

equally shifts both input and output common-mode levels.

Increasing the gain of the AD8352 increases the system noise and,

thus, decreases the SNR (3.5 dB at 100 MHz input for Av = 10 dB)

of the AD9445 when no filtering is used. Note that amplifier gains

from 3 dB to 18 dB, with proper selection of C

and R

, do not

appreciably affect distortion levels. These circuits, when configured

properly, can result in SFDR performance of better than 87 dBc

at 70 MHz and 82 dBc at 180 MHz input. Single-ended drive, with

appropriate C

and R

, give similar results for SFDR and third-

order intermodulation levels shown in these figures.

Placing antialiasing filters between the ADC and the amplifier

is a common approach for improving overall noise and broad-

band distortion performance for both band-pass and low-pass

applications. For high frequency filtering, matching to the filter

is required. The AD8352 maintains a 100 Ω output impedance

well beyond most applications and is well-suited to drive most

filter configurations with little or no degradation in distortion.

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AD8352ACPZ-R7

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RF Amplifier 2 GHZ Low Distortion RF/IF

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