Lattice Semiconductor Turbo Decoder User’s Guide
22
Appendix for LatticeSC™ FPGAs
Table 16. Performance and Utilization
1
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Turbo Decoder core targeting LatticeSC devices is
TURBO-DECO-SC-U3. Table 1 lists the parameter settings that are available for the Turbo Decoder. Use the IPex-
press software tool to help generate new configurations of this IP core. IPexpress is the Lattice IP configuration util-
ity, and is included as a standard feature of the ispLEVER design tools. Details regarding the usage of IPexpress
can be found in the IPexpress and ispLEVER help system. For more information on the ispLEVER design tools,
visit the Lattice web site at: www
.latticesemi.com/software.
IPexpress
User-Configurable Mode
SLICEs LUTs Registers I/Os
sysMEM™
EBRs
f
MAX
(MHz)
3GPP 2766 5356 2827 184 13 172
3GPP2 2747 5334 3066 249 27 197
CCSDS 4008 7791 4326 269 16 174
1. Performance and utilization characteristics are generated using LFSC3GA25E-7F900C, with Lattice's ispLEVER 7.1 SP1
software. When using this IP core in a different density, speed, or grade within the LatticeSC family, performance and utiliza-
tion may vary.
