Lattice Semiconductor Turbo Decoder User’s Guide
4
Block Diagram
Figure 2 shows a block diagram of the Turbo Decoder detailing the key components and the data paths between
these blocks.
Figure 2. Turbo Decoder Functional Block Diagram
Functional Description
The Turbo Decoder consists of four main components: control module, decoder, interleaver and memory buffers.
Control Module
The control module takes care of the interface, pipelining and handshake communication between various blocks
and I/O pins. Data and parity are read serially into the memory and it is assumed that the data is received in the
same order as it was transmitted from the encoder. Signal
blocksizeset(ipcfgset)
initializes the
blocksize
by specifying the size of the block to be input to the decoder. Input data can be given only when
rfi
is asserted.
Input data has to be qualified with
inpvalid
to be accepted by the core.
Decoder and Interleaver
Once the data is entered into the decoder, the decoder starts computing the LLR of each data symbol. The LLR is
computed for the block sequence twice, once using the non-interleaved data and the corresponding parity and then
using the interleaved data and the corresponding parity. One round of this computation is called an iteration. Each
iteration is divided into two sections, an ODD window and an EVEN window. The LLR for systematic parity is com-
puted during the ODD window and the LLR for interleaved data is computed during the EVEN window. When both
ODD and EVEN window computations are done, one iteration is complete. The user can set the number of itera-
tions for each block on the iterations pin. During the second half of the iteration, EVEN window, the LLR computed
in the first half is improved upon by using previous computations. Every window makes use of LLR information
computed in the previous window and tries to improve on the estimate of LLR. The interleaver is used in the second
half of iteration to generate the interleaved address. This address is used to address the data and parity memory to
read the interleaved data for the second half of the iteration. It is also used to address the LLR memory unit and get
the previously computed LLR information. At the end of one iteration, the decoder has a set of LLR for each input
data. The second iteration starts with again using the non-interleaved parity bits and data and the previously com-
puted LLR to get a new estimate of the LLR for the data. Once the decoder completes the number of iterations
required to be done, the LLR memory buffer has the final LLR values. The sign of the LLR values determines
whether the data is a ‘1’ or a ‘0’. A positive sign means the data value is a ‘1’, otherwise it is a ‘0’.
Memory
Data/Parity
Memory
Map
Decoder
LLR
Buffer
Data
Parity
write address
read address
Hard
Decision
Storage
(optional)
din
dout
write enable
write address
write enable
write address
write enable
Map
Decoder
Control Interleaver
LLR
Buffer
Hard
Decision
Storage
(optional)
