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Operation M48T86
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2.1.5 MOT (mode select)
The MOT pin offers the flexibility to choose between two bus types (see Figure 7 on
page 12). When connected to V
CC
, Motorola bus timing is selected. When connected to V
SS
or left disconnected, Intel bus timing is selected. The pin has an internal pull-down
resistance of approximately 20 KΩ.
2.1.6 DS (data strobe input)
The DS pin is also referred to as READ (RD). A falling edge transition on the Data Strobe
(DS) input enables the output during a a READ cycle. This is very similar to an Output
Enable (G
) signal on other memory devices.
2.1.7 E (chip enable input)
The chip enable pin must be asserted low for a bus cycle in the M48T86 to be accessed.
Bus cycles which take place without asserting E
will latch the addresses present, but no
data access will occur.
2.1.8 IRQ (interrupt request output)
The IRQ pin is an open drain output that can be used as an interrupt input to a processor.
The IRQ
output remains low as long as the status bit causing the interrupt is present and the
corresponding interrupt-enable bit is set. IRQ
returns to a high impedance state whenever
Register C is read. The RST
pin can also be used to clear pending interrupts. The IRQ bus
is an open drain output so it requires an external pull-up resistor to V
CC
.
2.1.9 RST (reset input)
The M48T86 is reset when the RST input is pulled low. With a valid V
CC
applied and a low
on RST
, the following events occur:
1. Periodic Interrupt Enable (PIE) bit is cleared to a zero (Register B; Bit 6);
2. Alarm Interrupt Enable (AIE) bit is cleared to a zero (Register B; Bit 5);
3. Update Ended Interrupt Request (UF) bit is cleared to a zero (Register C; Bit 4);
4. Interrupt Request (IRQF) bit is cleared to a zero (Register C Bit 7);
5. Periodic Interrupt Flag (PF) bit is cleared to a zero (Register C; Bit 6);
6. The device is not accessible until RST
is returned high;
7. Alarm Interrupt Flag (AF) bit is cleared to a zero (Register C; Bit 5);
8. The IRQ
pin is in the high impedance state
9. Square Wave Output Enable (SQWE) bit is cleared to zero (Register B; Bit 3); and
10. Update Ended Interrupt Enable (UIE) is cleared to a zero (Register B; Bit 4).
2.1.10 RCL (RAM clear)
The RCL pin is used to clear all 114 storage bytes, excluding clock and control registers, of
the array to FF(hex) value. The array will be cleared when the RCL
pin is held low for at least
100 ms with the oscillator running. Usage of this pin does not affect battery load. This
function is applicable only when V
CC
is applied.
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