M48T86PC1 Datasheet M48T86MH1F, M48T86PC1, M48T86MH1E | P19-P21

Obsolete Product(s) - Obsolete Product(s)

M48T86 Clock operations

19/36

3.10 Register A

3.10.1 UIP update in progress

The Update in Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is

'1,' the update transfer will soon occur (see Figure 9). When UIP is a '0,' the update transfer

will not occur for at least 244 µs. The time, calendar, and alarm information in RAM is fully

available for access when the UIP bit is '0.' The UIP bit is “Read only” and is not affected by

RST

. Writing the SET bit in Register B to a '1' inhibits any update transfer and clears the UIP

Status bit.

3.10.2 OSC0, OSC1, OSC2 oscillator control

These three bits are used to control the oscillator and reset the countdown chain. A pattern

of “010” enables operation by turning on the oscillator and enabling the divider chain. A

pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When “010”

is written, the first update begins after 500 ms.

3.10.3 RS3, RS2, RS1, RS0

These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the

divider output. The tap selected may be used to generate an output square wave (SQW pin)

and/or a periodic interrupt. The user may do one of the following:

1. Enable the interrupt with the PIE bit;

2. Enable the SQW output with the SQWE bit;

3. Enable both at the same time and same rate;

4. Enable neither.

Table 4 on page 18 lists the periodic interrupt rates and the square wave frequencies that

may be chosen with the RS bits. These four READ/WRITE bits are not affected by RST

Table 5. Register A MSB

Figure 9. Update period timing and UIP

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

UIP OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0

AI01651

UIP

UPDATE PERIOD (1sec)

tBUC tUC

Obsolete Product(s) - Obsolete Product(s)

Clock operations M48T86

20/36

3.11 Register B

3.11.1 SET

When the SET bit is a '0,' the update transfer functions normally by advancing the counts

once per second. When the SET bit is written to a '1,' any update transfer is inhibited and

the program may initialize the time and calendar bytes without an update occurring. READ

cycles can be executed in a similar manner. SET is a READ/WRITE bit which is not modified

by RST

or internal functions of the M48T86.

3.11.2 PIE: periodic interrupt enable

The Periodic Interrupt Enable bit (PIE) is a READ/WRITE bit which allows the Periodic

Interrupt Flag (PF) bit in Register C to cause the IRQ

pin to be driven low (see Figure 10 on

page 21 for the relationship between PIE and UIE). When the PIE bit is set to '1,' periodic

interrupts are generated by driving the IRQ

pin low at a rate specified by the RS3-RS0 bits

of Register A. A '0' in the PIE bit blocks the IRQ

output from being driven by a periodic

interrupt, but the Periodic Flag (PF) bit is still set at the periodic rate. PIE is not modified by

any internal M48T86 functions, but is cleared to '0' on RST

3.11.3 AIE: alarm interrupt enable

The Alarm Interrupt Enable (AIE) bit is a READ/WRITE bit which, when set to a '1,' permits

the Alarm Flag (AF) bit in Register C to assert IRQ

. An alarm interrupt occurs for each

second that the three time bytes equal the three alarm bytes including a “Don't care” alarm

code of binary 1XXXXXXX. When the AIE bit is set to '0,' the AF bit does not initiate the IRQ

signal. The RST

pin clears AIE to '0.' The internal functions of the M48T86 do not affect the

AIE Bit.

3.11.4 UIE: update ended interrupt enable

The Update Ended Interrupt Enable (UIE) bit is a READ/WRITE bit which enables the

Update End Flag (UF) bit in Register C to assert IRQ

. A transition low on the RST pin or the

SET bit going high clears the UIE bit.

3.11.5 SQWE: square wave enable

When the Square Wave Enable (SQWE) bit is set to a '1,' a square wave signal is driven out

on the SQW pin. The frequency is determined by the rate-selection bits RS3-RS0. When the

SQWE bit is set to '0,' the SQW pin is held low. The SQWE bit is cleared by the RST

pin.

SQWE is a READ/WRITE bit.

3.11.6 DM: data mode

The Data Mode (DM) bit indicates whether time and calendar information are in binary or

BCD format. The DM bit is set by the program to the appropriate format and can be read as

required. This bit is not modified by internal function or RST

. A '1' in DM signifies binary data

and a '0' specifies binary coded decimal (BCD) data.

Obsolete Product(s) - Obsolete Product(s)

M48T86 Clock operations

21/36

3.11.7 24/12

The 24/12 Control bit establishes the format of the hours byte. A '1' indicates the 24-hour

mode and a '0' indicates the 12-hour mode. This bit is READ/WRITE and is not affected by

internal functions or RST

3.11.8 DSE: daylight savings enable

The Daylight Savings Enable (DSE) bit is a READ/WRITE bit which enables two special

updates when set to a '1.' On the first Sunday in April, the time increments from 1:59:59AM

to 3:00:00 AM. On the last Sunday in October, when the time reaches 1:59:59 AM, it

changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a '0.' This

bit is not affected by internal functions or RST

Table 6. Register B MSB

Figure 10. Update-ended/periodic interrupt relationship

3.12 Register C

3.12.1 IRQF: interrupt request flag

The Interrupt Request Flag (IRQF) bit is set to a '1' when one or more of the following are

true:

PF = PIE = 1

AF = AIE = 1

UF = UIE = 1

(e.g., IRQF = PF*PIE+AF*AIE+UF*UIE)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

SET PIE AIE UIE SQWE DM 24/12 DSE

AI01652B

UIP

UPDATE PERIOD (1sec)

tPI

tPI tPI

tBUC tUC

Obsolete Product(s) - Obsolete Product(s)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

M48T86PC1

Mfr. #:

Buy M48T86PC1

Manufacturer:

STMicroelectronics

Description:

Real Time Clock 5 Volt PC Drop-In

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

M48T86PC1

M48T86PC1

Products related to this Datasheet