Obsolete Product(s) - Obsolete Product(s)
Clock operations M48T86
22/36
3.12.2 PF: periodic interrupt flag
The Periodic Interrupt Flag (PF) is a “Read only” bit which is set to a '1' when an edge is
detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic
rate. PF is set to a '1' independent of the state of the PIE Bit. The IRQ
signal is active and
will set the IRQF bit. The PF bit is cleared by a RST
or a software READ of Register C.
3.12.3 AF: alarm flag
A '1' in the AF (Alarm Interrupt Flag) bit indicates that the current time has matched the
alarm time. If the AIE bit is also a '1,' the IRQ
pin will go low and a '1' will appear in the IRQF
Bit. A RST
or a READ of Register C will clear AF.
3.12.4 UF: update ended interrupt flag
The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is
set to a '1,' the '1' in the UF bit causes the IRQF bit to be a '1.' This will assert the IRQ
pin.
UF is cleared by reading Register C or a RST
.
3.12.5 BIT 0 through 3: unused bits
Bit 3 through Bit 0 are unused. These bits always read '0' and cannot be written.
3.13 Register D
3.13.1 VRT: valid RAM and time
The Valid RAM and Time (VRT) bit is set to the '1' state by STMicroelectronics prior to
shipment. This bit is not writable and should always be a '1' when read. If a '0' is ever
present, an exhausted internal lithium cell is indicated and both the contents of the RTC
data and RAM data are questionable. This bit is unaffected by RST
.
3.13.2 BIT 0 through 6: unused bits
The remaining bits of Register D are not usable. They cannot be written and when read,
they will always read '0.'
Table 7. Register C MSB
Table 8. Register D MSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
IRQFPFAFUF0000
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
VRT0000000
Obsolete Product(s) - Obsolete Product(s)
