14
FN6756.1
December 10, 2015
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs of the Slave Address Byte are
the device identifier bits, and the device identifier bits are
“1101111”.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W
bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(refer to Figure 10).
After loading the entire Slave Address Byte from the SDA
bus, the ISL12058 compares the device identifier bits with
“1101111”. Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Address Byte is a 1 byte register
address. The register address is supplied by the master
device. On power-up, the internal address counter is set to
address 0h, so a current address read of the RTC array
starts at address 0h. When required, as part of a random
read, the master must supply the 1 Word Address Bytes as
shown in Figure 11.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. For a random read of the Clock/Control Registers,
the slave byte must be “1101111x” in both places.
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12058 responds with an ACK. At this time, the I
2
C
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 11). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W
bit set to “1”. After each of
the three bytes, the ISL12058 responds with an ACK. Then
the ISL12058 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 11).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 1Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
FIRST DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL12058
A
C
K
10011
A
C
K
R/W BIT = “0”
SIGNAL AT SDA
111
ADDRESS
BYTE
A
C
K
LAST DATA
BYTE
A
C
K
FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
SLAVE
ADDRESS BYTE
D7 D6 D5 D2D4 D3 D1 D0
A0A7 A2A4 A3 A1
DATA BYTE
A6 A5
1
10
1
1
1
R/W
1
REGISTER
ADDRESS
ISL12058
