4
FN6756.1
December 10, 2015
Absolute Maximum Ratings Thermal Information
Voltage on V
DD
Pin (respect to GND) . . . . . . . . . . . . . . . -0.2V to 4V
Voltage on IRQ
/F
OUT ,
SCL and SDA Pins
(respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 6V
Voltage on X1 and X2 Pins (respect to GND) . . . . . . . . . -0.2V to 4V
ESD Rating ((Per MIL-STD-883 Method 3014)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>350V
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Lead SOIC (Note 3) . . . . . . . . . . . . . 120 N/A
8 Lead MSOP (Note 3). . . . . . . . . . . . . 169 N/A
8 Lead µTDFN (Note 3) . . . . . . . . . . . . 160 N/A
8 Lead TDFN (Notes 4, 5) . . . . . . . . . . 52 7
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
DC Operating Characteristics – RTC Temperature = -40°C to +85°C unless otherwise stated.
SYMBOL PARAMETER CONDITIONS
MIN
(Note 8)
TYP
(Note 7)
MAX
(Note 8) UNITS NOTES
V
DD
Main Power Supply 1.8 3.6 V
V
DDT
Timekeeping Power Supply 1.4 1.8 V
I
DD1
Standby Supply Current V
DD
= 3.6V 600 950 nA 6, 12
V
DD
= 3.0V 500 nA
I
DD2
Timekeeping Current V
DD
= 1.8V 400 650 nA 6, 12
V
DD
= 1.4V 350 nA
I
DD3
Supply Current With I
2
C Active at
Clock Speed of 400kHz
V
DD
= 3.6V 15 40 µA 6
I
LI
Input Leakage Current on SCL -100 100 nA
I
LO
I/O Leakage Current on SDA -100 100 nA
IRQ
/F
OUT
V
OL
Output Low Voltage V
DD
= 1.8V, I
OL
= 3mA 0.4 V
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 8) TYP (Note 7)
MAX
(Note 8) UNITS NOTES
SERIAL INTERFACE SPECS
V
IL
SDA and SCL Input Buffer LOW
Voltage
-0.3 0.3 x V
DD
V
V
IH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x V
DD
5.5 V
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.04 x V
DD
V
V
PULLUP
Maximum Pull-up Voltage on SDA
during I
2
C Communication
V
DD
+ 2 V 11
V
OL
SDA Output Buffer LOW Voltage,
Sinking 3mA
V
DD
> 1.8V, V
PULLUP
= 5.0V 0 0.4 V
Cpin SDA and SCL Pin Capacitance T
A
= +25°C, f = 1MHz, V
DD
= 5V,
V
IN
= 0V, V
OUT
= 0V
10 pF 9, 10
f
SCL
SCL Frequency 400 kHz
ISL12058
5
FN6756.1
December 10, 2015
t
IN
Pulse width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max
spec is suppressed
50 ns
t
AA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
V
DD
, until SDA exits the 30% to
70% of V
DD
window
900 ns 11
t
BUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of V
DD
during a
STOP condition, to SDA crossing
70% of V
DD
during the following
START condition
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
DD
crossing
1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
DD
crossing
600 ns
t
SU:STA
START Condition Setup Time SCL rising edge to SDA falling
edge. Both crossing 70% of V
DD
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing
30% of V
DD
to SCL falling edge
crossing 70% of V
DD
600 ns
t
SU:DAT
Input Data Setup Time From SDA exiting the 30% to 70%
of V
DD
window, to SCL rising edge
crossing 30% of V
DD
100 ns
t
HD:DAT
Input Data Hold Time From SCL falling edge crossing
30% of V
DD
to SDA entering the
30% to 70% of V
DD
window
0 900 ns
t
SU:STO
STOP Condition Setup Time From SCL rising edge crossing
70% of V
DD
, to SDA rising edge
crossing 30% of V
DD
600 ns
t
HD:STO
STOP Condition Hold Time From SDA rising edge to SCL
falling edge. Both crossing 70% of
V
DD
600 ns
t
DH
Output Data Hold Time From SCL falling edge crossing
30% of V
DD
, until SDA enters the
30% to 70% of V
DD
window
0ns
t
R
SDA and SCL Rise Time From 30% to 70% of V
DD
20 + 0.1 x Cb 300 ns 9, 10
t
F
SDA and SCL Fall Time From 70% to 30% of V
DD
20 + 0.1 x Cb 300 ns 9, 10, 11
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 9, 10
Rpu SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by t
R
and
t
F
.
For Cb = 400pF, max is about
2k to~2.5k.
For Cb = 40pF, max is about 15k
to ~20k
1k 9, 10
NOTES:
6. IRQ
/F
OUT
inactive.
7. Typical values are for T = +25°C and 3.3V supply voltage.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
9. Limits should be considered typical and are not production tested.
10. These are I
2
C specific parameters and are not production tested, however, they are used to set conditions for testing devices to
validate specification.
11. Parts will work with SDA pull-up voltage above the V
PULLUP
limit but the t
AA
and t
F
in the I
2
C parameters are not guaranteed.
12. Specified at +25°C.
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 8) TYP (Note 7)
MAX
(Note 8) UNITS NOTES
ISL12058
6
FN6756.1
December 10, 2015
SDA vs SCL Timing
Symbol Table
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
WAVEFORM INPUTS OUTPUTS
Must be steady Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A Center Line is
High Impedance
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V
DD
= 3.0V, V
PULLUP
= 5.0V
SDA,
IRQ
/F
OUT
1533
100pF
5.0V
FOR V
OL
= 0.4V
AND I
OL
= 3mA
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V
DD
= 3.0V
ISL12058

ISL12058IRUZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock REAL TIME CLK W/ ALARM & TIMR FUNCTNS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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