25AA160/25LC160/25C160
DS21231E-page 10 1997-2012 Microchip Technology Inc.
3.5 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX160 is busy with a write operation. When set to a
‘
1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘
0’, the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the Status
register. This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for the RDSR timing sequence.
FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE
3.6 Write Status Register (WRSR)
The Write Status register (WRSR) instruction allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the Status
register. The array is divided up into four segments.
The user has the ability to write-protect none, one, two
or all four of the segments of the array. The partitioning
is controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP
pin. The
Write-Protect (WP
) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the program-
mable hardware write-protect feature. Hardware write
protection is enabled when WP
pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP
pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-7 for the WRSR timing sequence.
TABLE 3-2: ARRAY PROTECTION
7 654 3 2 1 0
WPEN X X X BP1 BP0 WEL WIP
SO
SI
CS
9101112131415
11000000
7654 210
instruction
data from Status register
High-impedance
SCK
0 2345671
8
3
BP1 BP0
Array Addresses
Write-Protected
0 0 none
0 1 upper 1/4
(0600h - 07FFh)
1 0 upper 1/2
(0400h - 07FFh)
11 all
(0000h - 07FFh)
