1997-2012 Microchip Technology Inc. DS21231E-page 7
25AA160/25LC160/25C160
3.0 FUNCTIONAL DESCRIPTION
3.1 Principles of Operation
The 25XX160 are 2048 byte Serial EEPROMs
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s PIC16C6X/7X
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using dis-
crete I/O lines programmed properly with the software.
The 25XX160 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
pin must
be low and the HOLD
pin must be high for the entire
operation. The WP
pin must be held high to allow
writing to the memory array.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other periph-
eral devices on the SPI bus, the user can assert the
HOLD input and place the 25XX160 in ‘HOLD’ mode.
After releasing the HOLD
pin, operation will resume
from the point when the HOLD
was asserted.
3.2 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX160
followed by the 16-bit address, with the five MSBs of
the address being "don’t care" bits. After the correct
READ instruction and address are sent, the data stored
in the memory at the selected address is shifted out on
the SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to
provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached (07FFh), the address counter rolls
over to address 0000h allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS
pin (Figure 3-1).
3.3 Write Sequence
Prior to any attempt to write data to the 25XX160, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS
low
and then clocking out the proper instruction into the
25XX160. After all eight bits of the instruction are trans-
mitted, the CS
must be brought high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS
low, issuing a WRITE instruc-
tion, followed by the 16-bit address, with the five MSBs
of the address being "don’t care" bits, and then the data
to be written. Up to 16 bytes of data can be sent to the
25XX160 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with
xxxx xxxx
xxxx
0000 and ends with xxxx xxxx xxxx 1111.
If the internal address counter reaches
xxxx xxxx
xxxx
1111 and the clock continues, the counter will
roll back to the first address of the page and overwrite
any data in the page that may have been written.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n
th
data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
TABLE 3-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WRDI 0000 0100 Reset the write enable latch (disable write operations)
WREN 0000 0110 Set the write enable latch (enable write operations)
RDSR 0000 0101 Read Status register
WRSR 0000 0001 Write Status register
25AA160/25LC160/25C160
DS21231E-page 8 1997-2012 Microchip Technology Inc.
FIGURE 3-1: READ SEQUENCE
FIGURE 3-2: BYTE WRITE SEQUENCE
FIGURE 3-3: PAGE WRITE SEQUENCE
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
0100000115 14 13 12 210
76543210
instruction 16-bit address
data out
High-impedance
SO
SI
CS
91011 2122232425262728293031
0000000115 14 13 12
21076543210
instruction 16-bit address data byte
High-impedance
SCK
0 2345671
8
Twc
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12
21076543210
instruction 16-bit address data byte 1
SCK
0 23456718
SI
CS
41 42 43 46 47
76543210
data byte n (16 max)
SCK
32 34 35 36 37 38 3933
40
76543210
data byte 3
76543210
data byte 2
44 45
1997-2012 Microchip Technology Inc. DS21231E-page 9
25AA160/25LC160/25C160
3.4 Write Enable (WREN) and Write
Disable (WRDI)
The 25XX160 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
FIGURE 3-4: WRITE ENABLE SEQUENCE
FIGURE 3-5: WRITE DISABLE SEQUENCE
SCK
02345671
SI
High-impedance
SO
CS
010000 01
SCK
0 2345671
SI
High-impedance
SO
CS
010000 01
0

25C160/P

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 2kx8 5V
Lifecycle:
New from this manufacturer.
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