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NCP1251ASN65T1G

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NCP1251
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16
enough current (30 mA) at low line will turn a converter in
fault into an auto-recovery mode since the SCR won’t
remain latched. To build a sufficient design margin, we
recommend to keep at least 60 mA flowing at the lowest input
line (80 V rms for 85 V minimum for instance). An excellent
solution is to actually combine X2 discharge and start-up
networks as proposed in Figure 13 of application note
AND8488/D.
Internal Over Power Protection
There are several known ways to implement Over Power
Protection (OPP), all suffering from particular problems.
These problems range from the added consumption burden
on the converter or the skip−cycle disturbance brought by
the current−sense offset. A way to reduce the power
capability at high line is to capitalize on the negative voltage
swing present on the auxiliary diode anode. During the
power switch on−time, this point dips to −NV
in
, N being the
turns ratio between the primary winding and the auxiliary
winding. The negative plateau observed on Figure 42 will
have an amplitude dependant on the input voltage. The idea
implemented in this chip is to sum a portion of this negative
swing with the 0.8 V internal reference level. For instance,
if the voltage swings down to −150 mV during the on time,
then the internal peak current set point will be fixed to 0.8 −
0.150 = 650 mV. The adopted principle appears in Figure 42
and shows how the final peak current set point is
constructed.
1
v(24)
464u 472u 480u 488u 496u
time (s)
−40.0
−20.0
0
20.0
40.0
v(24) (V)
1
on−time
1
v(24)
−40.0
−20.0
0
20.0
40.0
1
off−time
Figure 41. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time
N
1
(V
out
+V
f
)
−N
2
V
bulk
Let’s assume we need to reduce the peak current from
2.5 A at low line, to 2 A at high line. This corresponds to a
20% reduction or a set point voltage of 640 mV. To reach this
level, then the negative voltage developed on the OPP pin
must reach:
V
OPP
+ 640m * 800m + −160 mV
(eq. 6)
NCP1251
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17
VDD
ref
OPP
+
−
from FB
reset
CS
VCC
aux
RoppU
swings to:
Vout during toff
−N V in during ton
Iopp
R oppL
SUM2
K1
K2
0.8 V
$5%
ref = 0.8 V + VOPP
(VO P P is negativ e)
This p oin t will
be adjusted to
reduce the ref
at hi line to the
desired level.
Figure 42. The OPP Circuitry Affects the Maximum Peak Current Set Point by Summing a Negative Voltage to the
Internal Voltage Reference
Let us assume that we have the following converter
characteristics:
V
out
= 19 V
V
in
= 85 to 265 V
rms
N
1
= N
p
:N
s
= 1:0.25
N
2
= N
p
:N
aux
= 1:0.18
Given the turns ratio between the primary and the auxiliary
windings, the on−time voltage at high line (265 Vac) on the
auxiliary winding swings down to:
V
aux
+ −N
2
V
in,max
+ −0.18 375 + −67.5 V
(eq. 7)
To obtain a level as imposed by Equation 6, we need to
install a divider featuring the following ratio:
Div +
0.16
67.5
[ 2.4m
(eq. 8)
If we arbitrarily fix the pull−down resistor R
OPPL
to 1 kW,
then the upper resistor can be obtained by:
R
OPPU
+
67.5 * 0.16
0.16ń1k
[ 421 kW
(eq. 9)
If we now plot the peak current set point obtained by
implementing the recommended resistor values, we obtain
the following curve (Figure 43):
80%
Peak current
setpoint
V
bulk
375
100%
Figure 43. The Peak Current Regularly Reduces Down to 20% at 375 Vdc
The OPP pin is surrounded by Zener diodes stacked to
protect the pin against ESD pulses. These diodes accept
some peak current in the avalanche mode and are designed
to sustain a certain amount of energy. On the other side,
negative injection into these diodes (or forward bias) can
cause substrate injection which can lead to an erratic circuit
behavior. To avoid this problem, the pin is internally
clamped slightly below –300 mV which means that if more
current is injected before reaching the ESD forward drop,
then the maximum peak reduction is kept to 40%. If the
voltage finally forward biases the internal zener diode, then
care must be taken to avoid injecting a current beyond
–2 mA. Given the value of R
OPPU
, there is no risk in the
present example.
NCP1251
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18
Finally, please note that another comparator internally
fixes the maximum peak current set point to 0.8 V even if the
OPP pin is inadvertently biased above 0 V.
Frequency Foldback
The reduction of no−load standby power associated with
the need for improving the efficiency, requires a change to
the traditional fixed−frequency type of operation. This
controller implements a switching frequency foldback when
the feedback voltage passes below a certain level, V
fold
, set
around 1.5 V. At this point, the oscillator enters frequency
foldback and reduces its switching frequency. The peak
current setpoint follows the feedback pin until its level
reaches 1.05 V. Below this value, the peak current freezes to
V
fold
/4.2 (250 mV or 31% of the maximum 0.8 V setpoint)
and the only way to further reduce the transmitted power is
to reduce the operating frequency down to 26 kHz. This
value is reached at a voltage feedback level of 350 mV
typically. Below this point, if the output power continues to
decrease, the part enters skip cycle for the best noise−free
performance in no−load conditions. Figure 44 depicts the
adopted scheme for the part.
The NCP1251F version offers a means to improve
light−load efficiency by folding the switching frequency
sooner compared to the other versions. With the 1251 A, B
and C versions, the minimum frequency is reached for V
FB
equals 350 mV. With the 1251F, this minimum frequency
will be obtained at a feedback voltage equal to 1.5 V,
naturally offering a better efficiency for lighter load
conditions. Figure 45 portrays the specific foldback scheme
implemented in the NCP1251F.
F
sw
V
FB
V
CS
V
FB
65 kHz
26 kHz
350 mV
V
fold
3.4 V
V
fold
3.4 V
0.8 V
0.36 V
FB
V
freeze
[
0.25 V
1.05 V 1.5 V
1.5 V
max
min
max
min
V
fold,end
Frequency Peak current setpoint
V
FB
min
Figure 44. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an
Improved Performance at Light Load
[
Figure 45. with NCP1251F, the frequency foldback occurs sooner as the load gets lighter.
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NCP1251ASN65T1G

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers OCP OVP VCC LATCH
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