NCP1251
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19
Auto−Recovery Short−Circuit Protection
In case of output short−circuit or if the power supply
experiences a severe overloading situation, an internal error
flag is raised and starts a countdown timer. If the flag is
asserted longer than 100 ms, the driving pulses are stopped
and the V
CC
pin slowly goes down to around 7 V. At this
point, the controller wakes−up and the V
CC
builds up again
due to the resistive starting network. When V
CC
reaches
VCC
ON
, the controller attempts to re−start, checking for the
absence of the fault. If the fault is still there, the supply enters
another cycle of so−called hiccup mode. If the fault has
cleared, the power supply resumes normal operation. Please
note that the soft−start is activated during each of the re−start
sequence.
1
vcc
2
vdrv
3
ilprim
500u 1.50m 2.50m 3.50m 4.50m
time in seconds
445m
1.41
2.38
3.35
4.32
ilprim in amperes
−8.13
−2.12
3.89
9.90
15.9
vcc in volts
−11.5
−2.72
6.05
14.8
23.6
vdrv in volts
Plot1
2
1
3
cc
V (t)
DRV
V
p
L
I
SS
1
vcc
2
vdrv
3
ilprim
500u 1.50m 2.50m 3.50m 4.50m
time in seconds
445m
1.41
2.38
3.35
4.32
ilprim in amperes
−8.13
−2.12
3.89
9.90
15.9
vcc in volts
−11.5
−2.72
6.05
14.8
23.6
vdrv in volts
Plot1
2
1
3
cc
V
DRV
V
p
L
I
SS
Figure 46. An Auto−Recovery Hiccup Mode is Activated for Faults Longer than 100 ms
(t)
(t)
Slope Compensation
The NCP1251 includes an internal ramp compensation
signal. This is the buffered oscillator clock delivered only
during the on time. Its amplitude is around 2.5 V at the
maximum duty−cycle. Ramp compensation is a known
means used to cure sub harmonic oscillations in Continuous
Conduction Mode (CCM) operated current−mode
converters. These oscillations take place at half the
switching frequency and occur only during CCM with a
duty−cycle greater than 50%. To lower the current loop gain,
one usually injects between 50% and 100% of the inductor
downslope. Figure 47 depicts how internally the ramp is
generated. Please note that the ramp signal will be
disconnected from the CS pin, during the off time.
Rsense
Rcomp
20k
0V
2.5 V
CS
+
LEB
from FB
setpoint
latch
reset
ON
Figure 47. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation and
Stabilizes the Converter in CCM Operation.
NCP1251
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20
In the NCP1251 controller, the oscillator ramp features a
2.5 V swing reached at a 80% duty−ratio. If the clock
operates at a 65 kHz frequency, then the available oscillator
slope corresponds to:
S
ramp
+
V
ramp,peak
D
max
T
SW
+
2.5
0.8 15m
(eq. 10)
+ 208 kVńsor208mVńms
In our flyback design, let’s assume that our primary
inductance L
p
is 770 mH, and the SMPS delivers 19 V with
a N
p
:N
s
ratio of 1:0.25. The off−time primary current slope
S
p
is thus given by:
S
p
+
ǒ
V
out
) V
f
Ǔ
N
p
N
s
L
p
+
(
19 ) 0.8
)
4
770m
+ 103 kAńs
(eq. 11)
Given a sense resistor of 330 mW, the above current ramp
turns into a voltage ramp of the following amplitude:
S
sense
+ S
p
R
sense
+ 103k 0.33
(eq. 12)
+ 34 kVńsor34mVńms
If we select 50% of the downslope as the required amount
of ramp compensation, then we shall inject a ramp whose
slope is 17 mV/ms. Our internal compensation being of
208 mV/ms, the divider ratio (divratio) between R
comp
and
the internal 20 kW resistor is:
divratio +
17m
208m
+ 0.082
(eq. 13)
The series compensation resistor value is thus:
(eq. 14
)
R
comp
+
R
ramp
@
divratio
+
20k
0.082
[
1.6 k
W
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. We recommend
adding a small capacitor of 100 pF, from the current sense
pin to the controller ground for an improved immunity to the
noise. Please make sure both components are located very
close to the controller.
Latching Off the Controller
The OPP pin not only allows a reduction of the peak
current set point in relationship to the line voltage, it also
offers a means to permanently latch−off the part. When the
part is latched−off, the V
CC
pin is internally pulled down to
around 7 V and the part stays in this state until the user cycles
the V
CC
down and up again, e.g. by un−plugging the
converter from the mains outlet. It is important to note that
the SCR maintains its latched state as long as the injected
current stays above the minimum value of 30 mA. As the
SCR delatches for an injected current below this value, it is
the designer duty to make sure the injected current is high
enough at the lowest input voltage. Failure to maintain a
sufficiently high current would make the device auto
recover. A good design practice is to ensure at least 60 mA
at the lowest input voltage. The latch detection is made by
observing the OPP pin by a comparator featuring a 3 V
reference voltage. However, for noise reasons and in
particular to avoid the leakage inductance contribution at
turn off, a 1 ms blanking delay is introduced before the
output of the OVP comparator is checked. Then, the OVP
comparator output is validated only if its high−state duration
lasts a minimum of 600 ns. Below this value, the event is
ignored. Then, a counter ensures that 4 successive OVP
events have occurred before actually latching the part. There
are several possible implementations, depending on the
needed precision and the parameters you want to control.
The first and easiest solution is the additional resistive
divider on top of the OPP one. This solution is simple and
inexpensive but requires the insertion of a diode to prevent
disturbing the OPP divider during the on time.
D2
1N4148
4
5
1
OPP
Vlatch
10
8
9
VCC
aux.
winding
OPP
ROPPL
1k
RoppU
421k
11
R3
5k
C1
100p
OVP
Figure 48. A Simple Resistive Divider Brings the OPP Pin Above 3 V in Case of a V
CC
Voltage Runaway above
18 V
NCP1251
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21
First, calculate the OPP network with the above equations.
Then, suppose we want to latch off our controller when V
out
exceeds 25 V. On the auxiliary winding, the plateau reflects
the output voltage by the turns ratio between the power and
the auxiliary winding. In case of voltage runaway for our
19 V adapter, the plateau will go up to:
V
aux,OVP
+ 25
0.18
0.25
+ 18 V
(eq. 15)
Since our OVP comparator trips at a 3 V level, across the
1 kW selected OPP pulldown resistor, it implies a 3 mA
current. From 3 V to go up to 18 V, we need an additional
15 V. Under 3 mA and neglecting the series diode forward
drop, it requires a series resistor of:
R
OVP
+
V
latch
* V
VOP
V
OVP
ńR
OPPL
+
18 * 3
3ń1k
+
15
3m
+ 5kW
(eq. 16)
In nominal conditions, the plateau establishes to around
14 V. Given the divide−by−6 ratio, the OPP pin will swing
to 14/6 = 2.3 V during normal conditions, leaving 700 mV
margin. A 100 pF capacitor can be added between the OPP
pin and GND to improve noise immunity and avoid erratic
trips in presence of external surges. Do not increase this
capacitor too much otherwise the OPP signal will be affected
by the integrating time constant.
A second solution for the OVP detection alone, is to use
a Zener diode wired as recommended by.
D3
15V
4
5
1
OPP
Vlatch
10
8
9
VCC
aux.
winding
OPP
ROPPL
1k
ROPPU
421k
11
D2
1N4148
C1
22pF
OVP
Figure 49. A Zener Diode in Series with a Diode Helps to Improve the Noise Immunity of the System
For this configuration to maintain an 18 V level, we have
selected a 15 V Zener diode. In nominal conditions, the
voltage on the OPP pin is almost 0 V during the off time as
the Zener is fully blocked. This technique clearly improves
the noise immunity of the system compared to that obtained
from a resistive string as in Figure 48. Please note the
reduction of the capacitor on the OPP pin to 10 pF − 22 pF.
This capacitor is necessary because of the potential spike
coupling through the Zener parasitic capacitance from the
bias winding due to the leakage inductance. Despite the 1 ms
blanking delay at turn off. This spike is energetic enough to
charge the added capacitor C
1
and given the time constant,
could make it discharge slower, potentially disturbing the
blanking circuit. When implementing the Zener option, it is
important to carefully observe the OPP pin voltage (short
probe connections!) and check that enough margin exists to
that respect.
Over Temperature Protection
In a lot of designs, the adapter must be protected against
thermal runaways, e.g. when the temperature inside the
adapter box increases above a certain value. Figure 50
shows how to implement a simple OTP using an external
NTC and a series diode. The principle remains the same:
make sure the OPP network is not affected by the additional
NTC hence the presence of this isolation diode. When the
NTC resistance decreases as the temperature increases, the
voltage on the OPP pin during the off time will slowly
increase and, once it passes 3 V for 4 consecutive clock
cycles, the controller will permanently latch off.

NCP1251ASN65T1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers OCP OVP VCC LATCH
Lifecycle:
New from this manufacturer.
Delivery:
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