IS65WV12816ALL
IS65WV12816BLL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. B
11/09/07
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
128K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation:
36 mW (typical) operating
9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply:
1.65V to 2.2V V
DD (65WV12816ALL)
2.5V to 3.6V V
DD (65WV12816BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• 2CS Option Available
• Temperature Offerings:
Option A: 0 to 70
o
C
Option A1: –40 to +85
o
C
Option A2: –40 to +105
o
C
Option A3: –40 to +125
o
C
• Lead-free available
DESCRIPTION
The ISSI IS65WV12816ALL/ IS65WV12816BLL are high-
speed, 2M bit static RAMs organized as 128K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS65WV12816ALL and IS65WV12816BLL are packged
in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and
44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
NOVEMBER 2007
A0-A16
CS1
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
