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IS65WV12816BLL-55BLA3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
IS65WV12816ALL, IS65WV12816BLL
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
11/09/07
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS1 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB, UB
t
PWB
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
11
Rev. B
11/09/07
IS65WV12816ALL, IS65WV12816BLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
IS65WV12816ALL, IS65WV12816BLL
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
11/09/07
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
tWC
tSCS1
tSCS2
tAW
tHA
tPWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

IS65WV12816BLL-55BLA3

Mfr. #:
Buy IS65WV12816BLL-55BLA3
Manufacturer:
ISSI
Description:
SRAM 2M (128Kx16) 55ns Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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