Technical Note
13/20
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2011.08 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD8119FM-M
5. Selection of the output capacitor
Select the output capacitor Cout based on the requirement of the ripple voltage Vpp.
Vpp = × × + IL_MIN × RESR
Choose Cout that allows the Vpp to settle within the requirement. Allow some margin also, such as the tolerance of the
external components.
6. Selection of the input capacitor
A capacitor at the input is also required as the peak current flows between the input and the output in DC/DC conversion.
We recommend an input capacitor greater than 10µF with the ESR smaller than 100m. The input capacitor outside of
our recommendation may cause large ripple voltage at the input and hence lead to malfunction.
7. Phase Compensation Guidelines
In general, the negative feedback loop is stable when the following condition is met:
Overall gain of 1 (0dB) with a phase lag of less than 150º (i.e., a phase margin of 30º or more)
However, as the DC/DC converter constantly samples the switching frequency, the gain-bandwidth (GBW) product of
the entire series should be set to 1/10 the switching frequency of the system. Therefore, the overall stability
characteristics of the application are as follows:
Overall gain of 1 (0dB) with a phase lag of less than 150º (i.e., a phase margin of 30º or more)
GBW (frequency at gain 0dB) of 1/10 the switching frequency
Thus, to improve response within the GBW product limits, the switching frequency must be increased.
The key for achieving stability is to place fz near to the GBW.
Phase-lead fz = [Hz]
Phase-lag fp1 = [Hz]
Good stability would be obtained when the fz is set between 1kHz10kHz.
In buck-boost applications, Right-Hand-Plane (RHP) Zero exists. This Zero has no gain but a pole characteristic in
terms of phase. As this Zero would cause instability when it is in the control loop, so it is necessary to bring this zero
before the GBW.
fRHP= [Hz] I
LOAD
: Maximum Load Current
It is important to keep in mind that these are very loose guidelines, and adjustments may have to be made to ensure
stability in the actual circuitry. It is also important to note that stability characteristics can change greatly depending on
factors such as substrate layout and load conditions. Therefore, when designing for mass-production, stability should
be thoroughly investigated and confirmed in the actual physical design.
1
Fosc
1
2πCpcRpc
FB
A
COMP
V
out
Rpc
LED
Cpc
1
2πRLCout
2πI
LOAD
L
Vout+VIN/(Vout+VIN)
Vout
Vout+V
IN
Iout
Cout
Technical Note
14/20
www.rohm.com
2011.08 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD8119FM-M
8. Setting of the over-voltage protection
We recommend setting the over-voltage protection Vovp
1.2V to 1.5V greater than Vout which is adjusted by the
number of LEDs in series connection. Less than 1.2V may
cause unexpected detection of the LED open and short during
the PWM brightness control. For the Vovp greater than 1.5V,
the LED short detection may become invalid.
9. Setting of the soft-start
The soft-start allows minimization of the coil current as well as the overshoot of the output voltage at the start-up.
For the capacitance we recommend in the range of 0.001 0.1µF. For the capacitance less than 0.001µF may cause
overshoot of the output voltage. For the capacitance greater than 0.1µF may cause massive reverse current through the
parasitic elements of the IC and damage the whole device. In case it is necessary to use the capacitance greater than
0.1µF, ensure to have a reverse current protection diode at the Vcc or a bypass diode placed between the SS-pin and
the Vcc.
Soft-start time TSS
TSS = CSSX0.7V / 5µA [s] CSS: The capacitance at the SS-pin
10 Verification of the operation by taking measurements
The overall characteristic may change by load current, input voltage, output voltage, inductance, load capacitance,
switching frequency, and the PCB layout. We strongly recommend verifying your design by taking the actual
measurements.
2.0V/1.45V
1.7V/1.6V
OVP
Vo
ROVP2
ROVP1
Technical Note
15/20
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2011.08 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD8119FM-M
Power Dissipation Calculation
Power dissipation can be calculated as follows:
Pc(N) = ICC*VCC + 2*Ciss*VREG*Fsw*Vcc+[VLED*N+Vf*(N-1)]*ILED
I
CC
Maximum circuit current
V
CC
Supply power voltage
C
iss
External FET capacitance
V
sw
SW gate voltage
F
sw
SE frequency
V
LED
LED control voltage
N LED parallel numeral
ΔV
f
LED V
f
fluctuation
I
LED
LED output current
Sample Calculation:
Pc(4) = 10mA × 30V + 500pF × 5V × 300kHz × 30V + [1.0V × 4 + Vf × 3] × 100mA
Vf = 3.0V, Pc (4) = 322.5mW + 1.3W = 1622.5mW
Fig.16
Note 1: Power dissipation calculated when mounted on 70mm X 70mm X 1.6mm glass epoxy substrate (1-layer platform/copper thickness 18µm)
Note 2: Power dissipation changes with the copper foil density of the board.
The area of the copper foil becomes the total area of the heat radiation fin and the foot pattern (connected directly with IC) of this IC.
This value represents only observed values, not guaranteed values.
Pd=2200mW ( 968mW): Substrate copper foil density 3%
Pd=3200mW (1408mW): Substrate copper foil density 34%
Pd=3500mW (1540mW): Substrate copper foil density 60% (Value within parentheses represents power dissipation when Ta=95°C)
Note 3: Please design so that ambient temperature + self-generation of heat may become 150
or less because this IC is Tj=150.
Note 4: Please note the heat design because there is a possibility that thermal resistance rises from the examination result of the temperature cycle
by 20% or less.
0
500
1000
1500
2000
2500
00.511.522.533.5
LEDバラツキ⊿Vf[V]
ILED=5
0mA
ILED=1
00mA
ILED=1
50mA
Power Dissipation
Pd [mW]
LED Fluctuation ΔVf [V]
Ambient Temperature Ta[℃]
4
Power Dissipation Pd[W]
2
1
0 150 125 100 75 50 25
3
(3) 3.50W
(2) 3.20W
(1) 2.20W
(1) θja=56.8℃/W (Substrate copper foil density 3%)
(2) θja=39.1℃/W (Substrate copper foil density34%)
(3) θja=35.7℃/W (Substrate copper foil density60%)
95

BD8119FM-ME2

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Description:
LED Lighting Drivers Auto Grade LED Drvr
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