Technical Note
19/20
www.rohm.com
2011.08 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD8119FM-M
●Notes for use
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may
result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode)
when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider
adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC.
2) GND potential
Ensure that the GND pin is held at the minimum potential in all operating conditions.
3) Thermal Design
Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions.
4) Inter-pin shorts and mounting errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by poor
soldering or foreign objects may result in damage to the IC.
5) Operation in strong electromagnetic fields
Exercise caution when using the IC in the presence of strong electromagnetic fields as doing so may cause the IC to
malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to
stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be
turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent
damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
7) Ground wiring patterns
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused
by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage.
8) IC input pins and parasitic elements
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes
and/or transistors. For example (refer to the figure below):
Example of IC Structure
・When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
・When GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
9) Over-current protection circuits
An over-current protection circuit (designed according to the output current) is integrated into the IC to prevent damage in
the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected
overloads on the output. However, the IC should not be used in applications where operation of the OCP function is
anticipated or assumed
10) Thermal shutdown circuit (TSD)
This IC also incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within
the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power
dissipation limits, the rise in the chip's junction temperature T
j
will trigger the TSD circuit, shutting off all output power
elements. The circuit automatically resets itself once the junction temperature T
j
drops down to normal operating
temperatures. The TSD protection will only engage when the IC's absolute maximum ratings have been exceeded;
therefore, application designs should never attempt to purposely make use of the TSD function.
Pin A
Parasitic Elements
N
N
N
P
+
P
+
P
P Substrate
GND
Parasitic Element
Resistance
N
N
P
+
P
+
P
P substrate
GND
P
r
i
i
El
m
n
Pin B
Transistor (NPN)
C
B
E
N
GND
Pin A
Parasitic Element
Pin B
Other Adjacent Elements
E
B C
GND
