1 of 22 101000
FEATURES
Generates/detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systems
Operates at speeds from DC to 20 MHz
Programmable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 2
6
-1, 2
9
-1, 2
11
-1, 2
15
-1, 2
20
-1, 2
23
-1,
and 2
32
-1
Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in length
Large 32-bit error count and bit count
registers
Software programmable bit error insertion
Fully independent transmit and receive
sections
8-bit parallel control port
Detects test patterns with bit error rates up to
10
-2
PIN ASSIGNMENT
ORDERING INFORMATION
DS21372 (0
0
C to 70
0
C)
DS21372N (-40
0
C to +85
0
C)
DESCRIPTION
The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 operates at clock rates
ranging from DC to 20 MHz. This wide range of operating frequency allows the DS21372 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS21372 user-programmable pattern registers provide the unique ability to generate loopback
patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS21372 can
initiate the loopback, run the test, check for errors, and finally deactivate the loopback.
The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS21372 can be programmed to generate any pseudorandom pattern with length up
to 2
32
-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS21372 for applications requiring gap clocking such as Fractional-
T1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS21372 can insert single or 10
-1
to 10
-7
bit errors to verify equipment operation and connectivity.
DS21372
3.3V Bit Error Rate Tester (BERT)
www.dalsemi.com
TL
AD0
AD1
TEST
VSS
AD2
AD3
AD4
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
RL
RLOS
LC
VSS
VDD
INT
WR(R/W)
LE (AS)
AD5
AD6
AD7
VSS
VDD
BTS
RD(DS)
CS
TDATA
TDIS
TCLK
VSS
VDD
RCLK
RDIS
RDATA
DS21372
32-PIN TQFP
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
