DS21372
19 of 22
12.3 MOTOROLA BUS AC TIMING (BTS=1) FIGURE 5
t
DHW
t
DSW
t
AHL
t
ASL
t
CH
t
AHL
t
CS
t
ASL
t
RWS
t
DDR
t
DHR
t
RWH
t
CYC
PW
EH
t
ASED
PW
EL
t
ASD
PW
ASH
AS
DS
R/W
AD0-AD7
(
READ
)
CS
AD0-AD7
(WRITE)
DS21372
20 of 22
AC CHARACTERISTICS - RECEIVE SIDE
(0
0
C TO 70
0
C FOR DS21372; V
DD
=3.3V±10%)
-40
0
C to +85
0
C for DS21372N; V
DD
=3.3V±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
RCLK Period t
CP
50 ns
RCLK Pulse Width t
CH
t
CL
8
8
ns
ns
RDATA Set Up to RCLK Rising t
SU1
5ns
RDATA Hold from RCLK Rising t
HD1
0ns
RDIS Set Up to RCLK Rising t
SU2
5ns
RDIS Hold from RCLK Rising t
HD2
0ns
RL and LC Pulse Width t
WRL
25 ns
RCLK Rise and Fall Times t
R
, t
F
10 ns 1
AC CHARACTERISTICS - TRANSMIT SIDE
(0
0
C to 70
0
C for DS21372; V
DD
=3.3V±10%)
-40
0
C to +85
0
C for DS21372N; V
DD
=3.3V±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
TCLK Period t
CP
50 ns
TCLK Pulse Width t
CH
t
CL
8
8
Ns
ns
TDATA Delay from TCLK Rising t
DD
30 ns
TDIS Set Up to TCLK Rising t
SU
5ns
TDIS Hold from TCLK Rising t
HD
0ns
TL Pulse Width t
WTL
15 ns
TL Set Up to TCLK Rising t
STL
5ns
TL Hold Off from TCLK Rising t
HTL
0ns
TCLK Rise and Fall Time t
R
, t
F
10 ns 1
NOTE:
1. The maximum rise and fall time is either 10 ns or 10% of t
CP
whichever is less.
DS21372
21 of 22
RECEIVE AC TIMING Figure 6
TRANSMIT AC TIMING Figure 7
NOTE:
When TDIS is high about the rising edge of TCLK, TDATA will not be updated and will be held with the
previous valve until TDIS is low about the rising edge of TCLK.
TRANSMIT AC TIMING FOR THE TL INPUT Figure 8
NOTE:
The rising edge of TL causes the internal pattern generation circuitry to be reloaded; the first bit of the
new pattern (the shaded one) will appear after two TCLK periods.

DS21372TN

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Communication ICs - Various 3.3V Bit Error Rate Tester (BERT)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet