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DS21372TN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
DS21372
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DETAILED PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
1TL ITransmit Load. A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should
be tied to V
SS
if not used. See Figure 8 for timing information.
2 AD0 I/O Data Bus. An 8-bit multiplexed address/data bus.
3 AD1 I/O Data Bus. An 8-bit multiplexed address/data bus.
4 TEST I
Test. Set high to 3-state all output pins (INT , ADx, TDATA, RLOS).
Should be tied to V
SS
to enable all outputs.
5V
SS
- Signal Ground. 0.0V. Should be tied to local ground plane.
6 AD2 I/O Data Bus. An 8-bit multiplexed address/data bus.
7 AD3 I/O Data Bus. An 8-bit multiplexed address/data bus.
8 AD4 I/O Data Bus. An 8-bit multiplexed address/data bus.
9 AD5 I/O Data Bus. An 8-bit multiplexed address/data bus.
10 AD6 I/O Data Bus. An 8-bit multiplexed address/data bus.
11 AD7 I/O Data Bus. An 8-bit multiplexed address/data bus.
12 V
SS
- Signal Ground. 0.0V. Should be tied to local ground plane.
13 V
DD
- Positive Supply. 3.3V.
14 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the RD (DS),
ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
15
RD (DS)
I
Read Input (Data Strobe).
16
CS
I Chip Select. Must be low to read or write the port.
17 ALE(AS) I Address Latch Enable (Address Strobe). A positive going edge serves
to demultiplex the bus.
18
WR (R/ W )
I
Write Input (Read/Write).
19
INT
O Alarm Interrupt. Flags host controller during conditions defined in
Status Register. Active low, open drain output.
20 V
DD
- Positive Supply. 3.3V.
21 V
SS
- Signal Ground. 0.0V. Should be tied to local ground plane.
22 LC I
Load Count. A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR’ed with control bit PCR.4.
Should be tied to V
SS
if not used.
23 RLOS O Receive Loss Of Sync. Indicates the real time status of the receive
synchronizer. Active high output.
DS21372
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PIN SYMBOL TYPE DESCRIPTION
24 RL I Receive Load. A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR’ed with control bit PCR.3. Should be tied to V
SS
if not used.
25 RDATA I
Receive Data. Received NRZ serial data, sampled on the rising edge of
RCLK.
26 RDIS I Receive Disable. Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to V
SS
if not used. See Figure 6 for timing information. All receive side
operations are disabled when RDIS is high.
27 RCLK I
Receive Clock. Input clock from transmission link. 0 to 20 MHz. Can
be a gapped clock. Fully independent from TCLK.
28 V
DD
- Positive Supply. 3.3V.
29 V
SS
- Signal Ground. 0.0V. Should be tied to local ground plane.
30 TCLK I Transmit Clock. Transmit demand clock. 0 to 20 MHz. Can be a
gapped clock. Fully independent of RCLK.
31 TDIS I Transmit Disable. Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to V
SS
if not used. See Figure 7 for timing information. All transmit
side operations are disabled when TDIS is high.
32 TDATA O Transmit Data. Transmit NRZ serial data, updated on the rising edge of
TCLK.
DS21372 REGISTER MAP Table 2
ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME
00 R/W Pattern Set Register 3. 0C R Bit Error Counter Register 3.
01 R/W Pattern Set Register 2. 0D R Bit Error Counter Register 2.
02 R/W Pattern Set Register 1. 0E R Bit Error Counter Register 1.
03 R/W Pattern Set Register 0. 0F R Bit Error Counter Register 0.
04 R/W Pattern Length Register. 10 R Pattern Receive Register 3.
05 R/W Polynomial Tap Register. 11 R Pattern Receive Register 2.
06 R/W Pattern Control Register. 12 R Pattern Receive Register 1.
07 R/W Error Insert Register. 13 R Pattern Receive Register 0.
08 R Bit Counter Register 3. 14 R Status Register.
09 R Bit Counter Register 2. 15 R/W Interrupt Mask Register.
0A R Bit Counter Register 1. 1C R/W Test Register (see note 1)
0B R Bit Counter Register 0.
NOTE:
1. The Test Register must be set to 00 hex to insure proper operation of the DS21372.
DS21372
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2. PARALLEL CONTROL INTERFACE
The DS21372 is controlled via a multiplexed bi-directional address/data bus by an external
microcontroller or microprocessor. The DS21372 can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics for more details. The multiplexed bus on the DS21372 saves pins because the
address information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE (AS), at which time the DS21372
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during
the later portion of the DS or WR pulses. In a read cycle, the DS21372 outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high
impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The
DS21372 can also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update
counters and load transmit and receive pattern registers. At slow clock rates, sufficient time must be
allowed for these port operations.
3. PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB) (LSB)
PS31 PS30 PS29 PS28 PS27 PS26 PS25 PS24 PSR3 (addr.=00 Hex)
PS23 PS22 PS21 PS20 PS19 PS18 PS17 PS16 PSR2 (addr.=01 Hex)
PS15 PS14 PS13 PS12 PS11 PS10 PS9 PS8 PSR1 (addr.=02 Hex)
PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PSR0 (addr.=03 Hex)
4. PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

DS21372TN

Mfr. #:
Buy DS21372TN
Manufacturer:
Maxim Integrated
Description:
Communication ICs - Various 3.3V Bit Error Rate Tester (BERT)
Lifecycle:
New from this manufacturer.
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