13
LT1803/LT1804/LT1805
180345f
APPLICATIO S I FOR ATIO
WUUU
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Output Overdrive Recovery
Circuit Description
The LT1803/LT1804/LT1805 have input and output signal
ranges from the negative power supply to the positive
power supply. Figure 1 depicts a simplified schematic of
one amplifier. The input stage is comprised of two differ-
ential amplifiers, a PNP stage Q1/Q2 and an NPN stage Q3/
Q4 that are active over the different ranges of the common
mode input voltage. The PNP differential pair is active
between the negative supply and approximately 1.3V
below the positive supply. As the input voltage moves
toward the positive supply, the transistor Q5 will steer the
tail current I
1
to the current mirror Q6/Q7 activating the
NPN differential pair. The PNP pair becomes inactive for
the rest of the input common mode range up to the positive
supply. Also at the input stage, devices Q18 and Q19 act
to cancel the bias current of the PNP input pair. When Q1
and Q2 are active, the current in Q16 is controlled to be the
same as the current in Q1 and Q2; therefore, the base
current of Q16 is nominally equal to the base current of the
input devices. The base current of Q16 is then mirrored by
devices Q17 through Q19 to cancel the base current of the
input devices Q1 and Q2.
A pair of complementary common emitter stages Q14/
Q15 that enable the output to swing from rail-to-rail
constructs the output stage. The capacitors C1 and C2
form the local feedback loops that lower the output
impedance at high frequency. The LT1803/LT1804/LT1805
are fabricated on Linear Technology’s proprietary high
speed complementary bipolar process.
Power Dissipation
There is a need to ensure that the die’s junction tempera-
ture does not exceed 150°C. Junction temperature T
J
is
calculated from the ambient temperature T
A
, power dissi-
pation P
D
and thermal resistance θ
JA
:
T
J
= T
A
+ (P
D
• θ
JA
)
The power dissipated in the IC is a function of the supply
voltage, amplifier current, output voltage and output cur-
rent. For a given supply voltage, the worst-case power
dissipation, P
DMAX
, occurs when the output current and
voltage drop in the amplifier product is maximized. For
example, if the amplifier is sourcing a constant current
then the P
DMAX
occurs when the output voltage is at about
V
S
–
. On the other hand, for a given load resistance to
ground, the P
DMAX
will occur when the output voltage is at
half of either supply voltage. P
DMAX
for a given resistance
to ground is given by:
P
DMAX
= (V
S
+
– V
S
–
) I
SMAX
+ (V
S
/2)
2
/R
L
Example: An LT1804 in an SO-8 package operating on ±5V
supplies and driving a 100Ω load to ground, the P
DMAX
per
amplifier is given by:
P
DMAX
= (10 • 3.25mA) + (2.5)
2
/100 = 0.0425 + 0.0625
= 0.095W
I
SMAX
is approximated for a typical part from the Supply
Currrent vs Supply Voltage graph.
±5V Large-Signal Response ±5V Small-Signal Response
180345 G39
V
IN
1V/DIV
V
OUT
2V/DIV
0V
100ns/DIV
V
S
= 5V, 0V
A
V
= 2
R
L
= 1k
180345 G38
50mV/DIV
0V
50ns/DIV
V
S
= ±5V
A
V
= 1
R
L
= 1k
180345 G37
2V/DIV
0V
200ns/DIV
V
S
= ±5V
A
V
= 1
R
L
= 1k
